MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 425

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

IO
10-38
TF=0 is the false condition specifier. The TF bit is only relevant for null
The MC68030 processes a null primitive with C A = I in the same manner
whether executing a general or conditional category coprocessor instruction.
the response CIR again without servicing any pending interrupts.
A null, CA=0 primitive provides a condition evaluation indicator to the main
The main processor completes the execution of a conditional category co-
completion of processing.
to read the response CIR until it receives a null, CA=0, PF= 1 primitive, and
then performs trace exception processing. When IA = 1, the main processor
That is, PF= 1 indicates that the coprocessor has completed all processing
associated with an instruction.
a conditional category instruction. TF = 1 is the true condition specifier, and
primitives with CA=0 that are used by the coprocessor during the execution
of a conditional instruction.
processor services pending interrupts (using a mid-instruction stack frame,
sets CA to one and IA to zero in the null primitive, the main processor reads
processor during the execution of a conditional instruction and ends the
dialogue between the main processor and coprocessor for that instruction.
processor instruction when it receives the primitive. The PF bit is not relevant
during conditional instruction execution since the primitive itself implies
Usually, when the main processor reads any primitive that does not have
CA= 1 while executing a general category instruction, it terminates the dia-
logue between the main processor and coprocessor. If a trace exception is
pending, however, the main processor does not terminate the instruction
dialogue until it reads a null, CA=0, PF=I primitive from the response CIR
services pending interrupts before reading the response CIR again.
Bit [1], the PF bit, shows the "processing finished" status of the coprocessor.
Bit [0], the TF bit, indicates the true/false condition during the execution of
If the coprocessor sets CA and IA to one in the null primitive, the main
refer to Figure 10-43) and reads the response CIR again. If the coprocessor
(refer to 10.5.2.5 TRACE EXCEPTIONS). Thus, the main processor continues
MC68030 USER'S MANUAL
MOTOROLA