MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 484
MC68030RC40C
Manufacturer Part Number
MC68030RC40C
Description
IC MPU 32BIT ENHANCED 128-PGA
Manufacturer
Freescale Semiconductor
Specifications of MC68030RC40C
Processor Type
M680x0 32-Bit
Speed
40MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
128-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
40MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
128
Package Type
PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Quantity
Price
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MOTOROLA
The next example is the data cache hit example from 11.4 EFFECT OF DATA
timing. The first is the timing from the appropriate table. The second is the
timing adjusted for a data cache hit. The third adds wait states only to write
T h e t h i r d
Using the general Equation (11-2), calculate as follows:
CACHE with two wait states per cycle (four-clock read/write). Hits in the data
cache and instruction cache are assumed. Three lines are shown for each
operat/ons, since the read operations hit in the cache and cause no delay.
e c u t i o n
Execution Time
t i m e ;
l i n e f o r e a c h t i m i n g is u s e d t o c a l c u l a t e
it is s h o w n
= 8 + [ 1 0 - min(4,2)] - [ 1 6 - rain(4,2)] +
= CCea 1 + [CC°Pl - m i n ( H ° P l ,Teal )] + [CCea2 - min(Hea2,T°P 1 )] +
8 + 8 + 1 4 + 5 + 1
[CCoP2 - min(HoP2,Tea2) ] - [CCea 3 - min(Hea3,ToP2)] +
[CCoP3 - min(HoP3,Tea3) ] - !CCea 4 - min(Hea4,ToP3)] +
[CCoP5 - min(HoP5,Tea5) ]
[5 - min(0,2)] + [4 - min(lO,3)] + [18 - min(6,0)] + [8 - rain(14,2)] +
[ 1 8 - min(6,0)] -~ [14 - rain(6,0)] +
[CCop 4 - min(HoP4,Tea4)] - !CCea 5 - min(Hea5,ToP4)] +
[ 2 4 - min(2,0)]
116 clock periods
MC68030 USER'S MANUAL
2.
3.
4.
1,
in b o l d f a c e
ADD.L
AND.L
TAS
MOVE.L
- 1 8 - - 6 + 1 8 + 1 4 + 2 4
Instruction
t y p e .
DI,([A2])
(A6),(8,A1)
(A3) +
-(A1),D1
t h e i n s t r u c t i o n
c a c h e
11-21
e x -
11
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