MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 456

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
10.5.2.3 PRIVILEGE VIOLATIONS.
10.5.2.4 cpTRAPcc INSTRUCTION TRAPS.
:
i t executes an RTE to return from the handier.
following the cpTRAPcc instruction. The processing associated with the
tempts to restart the instruction during which the exception occurred after
the information contained in the six-word stack frame. If the exception han-
The exception handler should also check the copy of the status register on
the stack to determine whether tracing is on. If tracing is on, the trace ex-
ception processing should also be emulated. Refer to 8.1.7 Trace Exception
for additional information.
and cpRESTORE instructions and, also, from the supervisor check coproces-
sor response primitive. The main processor initiates privilege violation ex-
ception processing if it attempts to execute either the cpSAVE or cpRESTORE
the coprocessor associated with the cpSAVE or cpRESTORE instructions.
when it reads the supervisor check primitive, it aborts the coprocessor in-
struction in progress by writing an abort mask (refer to 10.3.2 Control CIR)
to the control CIR. The main processor then performs privilege violation
exception processing.
cessing using the four-word pre-instruction stack frame (refer to Figure
exception handler does not modify the stack frame, the main processor at-
stack frame (refer to Figure 10-45) and the trap exception vector number 7.
The scanPC field of this stack frame contains the address of the instruction
cpTRAPcc instruction can then proceed, and the exception handler can locate
any immediate operand words encoded in the cpTRAPcc instruction using
dler does not modify the stack frame, the main processor executes the in-
struction f o l l o w i n g the cpTRAPcc instruction after it executes an RTE
instruction when it is in the user state (S=0 in status register). The main
processor initiates this exception processing prior to any communication with
If the main processor is executing a coprocessor instruction in the user state
If a privilege violation occurs, the main processor initiates exception pro-
10-41) and the privilege violation exception vector number 8. Thus, if the
instruction, the coprocessor returns the TRUE condition indicator to the main
processor with a null primitive, the main processor initiates trap exception
processing. The main processor uses the six-word post-instruction exception
instruction to exit from the handler.
MC68030 USER'S MANUAL
Privilege violations can result from the cpSAVE
If, during the execution of a cpTRAPcc
10-69
1 i