MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 40

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

M O T O R O L A
NOTES:
Absolute
Register Indirect
Register Indirect with Index
Memory Indirect
Program Counter Indirect with Displacement
Program Counter Indirect with Index
Program Counter Memory Indirect
Immediate
Register Direct
8, d16 -
(data) -
Address Register Direct
Address Register Indirect
Address Register Indirect with Pes';r~crement
Address Register Indirect with P~ececrement
Address Register Indirect with D:splacement
Address Register Indirect with Incex tS-Bit Displacement)
Address Register Indirect with Index (Base Displacement)
Absolute Short
Absolute Long
Data Register Direct
Memory Indirect Postindexed
Memory Indirect Preindexed
PC Indirect with Index (8-Bit Displacement)
PC Indirect with Index (Base Displacement)
PC Memory Indirect Postindexed
PC Memory Indirect Preindexed
An =
Xn =
Dn =
b d =
o d =
PC -
() =
[ ] =
Address Register, A0-A7
A twos-complement or sign-extended displacement; added as part of the
effective address calculation; size is 8 (d 8) or 16 (d16) bits; when omitted,
assemblers use a value of zero.
Address or data register used as an index register; form is Xn.SIZE*SCALE,
where SIZE is .W or .L (indicates index register size) and SCALE is 1, 2, 4,
or 8 (index register is multiplied by SCALE); use of SIZE and/or SCALE is
optional.
A twos-complement base displacement; when present, size can be 16 or
32 bits.
Outer displacement, added as part of effective address calculation after
any memory indirection; use is opt;ona[ with a size of 16 or 32 bits.
Data Register, D0-D7
Program Counter
Immediate value of 8, 16, or 32 bi's
Effective Address
Use as indirect access to long-word address.
MC68030 USER'S M A N U A L
Table 1-1. Addressing Modes
Addressing Modes
An
Dn
(An)
(An) +
(dl 6,An)
(bd,An,Xn)
([bd,An],Xn,od)
([bd,An,Xn],od)
(d16,PC)
(xxx).W
(xxx)./
#(data)
(d8,PC,Xn)
(bd,PC,Xn)
([bd,PC],Xn,od)
([bd,PC,Xn],od)
- (An)
(d8,An,Xn)
Syntax
1-11