MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 474

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

11.3.4 A c t u a l I n s t r u c t i o n - C a c h e - C a s e
MOTOROLA
sumes no overlap. Therefore, the actual execution time of an instruction
factor in the effect of wait states for the no-cache case, refer to 11.5 EFFECT
OF WAIT STATES.
The overall execution time for an instruction may depend on the overlap
with the previous and following instructions. Therefore, to calculate instruc-
tion execution time estimations, the entire code sequence to be evaluated
for the entire sequence. The formula for this calculation is:
where:
The instruction-cache-case time for most instructions is composed of the
average no-cache-case timing of the given instructions also gives 16 clocks
( 9 + 7 = 16 clocks). It should be noted again that the no-cache-case time as-
stream may be less than that given by adding the no-cache-case times. To
must be analyzed as a whole. To derive the actual instruction-cache-case
execution times for an instruction sequence (under the assumptions listed
in 11.6 INSTRUCTION TIMING TABLES), the instruction-cache-case times
listed in the tables must be used, and the proper overlap must be subtracted
more specific formula is:
where:
instruction-cache-case time for the effective address calculation (CCea) over-
lapped with the instruction-cache-case time for the operation (CCop). The
T n is the tail time for an instruction,
CC n is the instruction-cache-case time for an instruction,
H n is the head time for an instruction, and
CCean is the effective address time for the instruction-cache case,
CCopn is the instruction-cache-case time for the operation portion of an
Tea n is the tail time for the effective address of an instruction,
Top n is the tail time for the operation portion of an instruction,
min(a,b) is the m i n i m u m of parameters a and b.
HoPn is the head time for the operation portion of an instruction,
Hea n is the head time for the effective address of an instruction, and
min(a,b) is the minimum of parameters a and b.
CCeal + [CCopl - min(HoPl,Tea 1 )] + [CCea2 - min(Hea2,Top 1 )] +
instruction,
[CCoP2 - min(Hop2,Tea2)] + [CCea 3 - min(Hea3,Top2)] + . . .
CC 1 + [CC 2 - min(H2,T 1 )] + [(CC 3 - min(H3,T2)] + . . .
MC68030 USER'S MANUAL
Execution T i m e C a l c u l a t i o n s
(11-2)
(11-1 )
11-11