MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 589

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

INDEX-6
Instruction Trace, Real-Time, 12-39-12-43
Instruction Trap Exception, 8-9
IBE Bit, 6-22
Identification Code, Coprocessor, 10-4
Illegal Instruction Exception, 8-9
Immediate Data, 2-21
Index, Signal, 5-2
Indexed Addressing, 2-26
Indirect Absolute Memory Addressing, 2-28
Indirect Addressing, 2-28
Indirection, 9-34
Information, Ordering, 14-1
Initial Reset Timing, 7-105
Initial Shift Count, 9-69
Input Delay, 7-2
Instruction,
Instruction Address CIR, 10-33
Instruction Boundary Signals, 12-37
Instruction Burst Enable Bit, 6-22
Instruction Cache, 1-16, 6-1, 6-4, 11-4
Instruction Description
Instruction Fetch Pending Buffer, 11-5
Instruction Format, 3-1
Instruction Set, 1-13
Instruction Timing Tables, 11-24
CAS, 7-43,
Compare and Swap, 7-43
Coprocessor Context Save, 10-25
cpBcc, 10-14
cpDBcc, 10-17
cpRESTORE, 10-27
cpSAVE, 10-25
cpScc, 10-15
cpTRAPcc, 10-18
Set on Coprocessor Condition, 10-15
STOP, 8-14
TAS, 7-43
Test and Set, 7-43
Test Coprocessor Condition, Decrement and
Trap on Coprocessor Condition, 10-17
Example, 9-36
BKPT, 7-74, 8-22
Branch on Coprocessor Condition, 10-13
Breakpoint, 7-74, 8-22
CAS2, 7-43
Coprocessor Context Restore, 10-27
Move Address Space, 7-74
MOVES, 7-74
No Operation, 7-95
NOP, 7-95
Case, 11-6
Format, 3-18
Notation, 3-3
Summary, 3-18-3-24
Branch, 10-13
MC68030 USER'S MANUAL
Jump Effective Address Timing Table, 11-35
IPEND Signal, 5-8, 8-17, 8-18
IPL0-1PL2 Signals, 5-8, 7-69ff, 8-15
Late Bus Error,
Late Retry Operation, Burst, Timing, 7-92
Latency,
Levels, Interrupt, 8-15
Limit Check Procedure Flowchart, 9-43
Limit Fields, 9-70
Internal Microsequencer Status Signal, 5-10, 7-94,
Internal Operand Representation, 7-8
Internal to External Data Bus Multiplexer, 7-11
Interrupt Acknowledge Cycle, 7-69
Interrupt
Interrupt Pending Signal, 5-8, 8-17, 8-18
Interrupt Priority Level Signals, 5-8, 7-69ff, 8-15
Invalid Format Word, 10-23
Integer Arithmetic Instructions, 3-5
Interactions, Cache, 7-26
Interface,
Instructions,
STERM, Timing, 7-86
Third Access, Timing, 7-87
With DSACKx, Timing, 7-85
Interrupt, 11-61
Timing, 7-72
Cycle, Spurious, 7-74
Exception, 8-14, 10-71
Latency, 11-61
Levels, 8-15
Bus Arbitration, 11-62
Shift, 3-7
System Control, 3-12
Coprocessor, 10-1, 10-5
Memory, 12-11
Flowchart, 7-71
Coprocessor, 3-21
Data Movement, 3-4
Integer Arithmetic, 3-5
Logical, 3-6
MMU, 3-13, 9-62
Multiprocessor, 3-13
Privileged, 8-11
Program Control, 3-8
Rotate, 3-7
Binary Coded Decimal, 3-10
Bit Field, 3-9
Bit Manipulation, 3-8
Conditional, 10-12
General, 10-9
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