MC68030RC40C Freescale Semiconductor, MC68030RC40C Datasheet - Page 220

• Manufacturer Part Number: MC68030RC40C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC40C

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 40MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.3.7 Burst Operation Cycles
MOTOROLA
o n the alignment for a data access, the MC68030 may attempt to fill two
The MC68030 supports a burst mode for filling the on-chip instruction and
The MC68030 provides a set of handshake control signals for the burst mode.
When a miss occurs in one of the caches, the MC68030 initiates a bus cycle
to obtain the required data or instruction stream fetch. If the data or instruc-
tion can be cached, the MC68030 attempts to fill a cache entry. Depending
The mechanism that asserts the CBREQ signal for burstable cache entries is
State 7
data caches.
cache entries. The processor may also assert CBREQ to request a burst fill
operation. That is, the processor can fill additional entries in the line. The
enabled by the data burst enable (DBE) and instruction burst enable (IBE)
respectively. Either of the following conditions cause the MC68030 to initiate
same cache line. Refer to 6.1.3.1 SINGLE ENTRY MODE for details.
MC68030 allows a burst of as many as four long words.
bits of the cache control register (CACR) for the data and instruction caches,
a cache burst request (and assert CBREQ) for a cachable read cycle:
However, the MC68030 does not assert CBREQ during the first portion of a
misaligned access if the remainder of the access does not correspond to the
The processor negates AS (and DS, if necessary) during $7. It holds the
address and data valid during $7 to simplify memory interfaces. R/W and
cycle.
The external device must negate STERM within two clock periods after
asserting it, or the processor may inadvertently use STERM for the next
bus cycle.
• The logical address and function code signals of the current instruction
• All four long words corresponding to the indexed tag i n t h e appropriate
FC0-FC2 also remain valid throughout $7.
If more than one write cycle is required, $8-$11 are repeated for each write
or data fetch do not match the indexed tag field in the respective in-
struction or data cache.
cache are marked invalid.
MC68030 USER'S MANUAL
7-59
7