MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 167

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7
. 7
7.2 D A T A TRANSFER M E C H A N I S M
7-6
7.2.1 Dynamic Bus Sizing
taneously in lieu of or in conjunction with the DSACKx or STERM signals.
to a 32-bit port. Refer to 7.3.2 Asynchronous Write Cycle for timing relation-
this section and in MC68030EC/D, MC68030 E/ectr/ca/Specff/cat/ons. Addi-
tionally, the BERF~ and HALT signals can be asserted together to indicate a
vector number to locate an interrupt handler routine. AVEC is ignored during
The MC68030 architecture supports byte, word, and long-word operands
chronous bus cycles to and from 32-bit ports, terminated by STERM. Byte,
word, and long-word operands can be located on any byte boundary, but
When the processor requests a burst mode fill operation, it asserts the cache
the assertion of STERM causes the processor to latch the data. During a write
ships of STERM.
The bus error (BERR) signal is also a bus cycle termination indicator and can
Finally, the autovector (AVEC) signal can be used to terminate interrupt ac-
knowledge cycles, indicating that the MC68030 should internally generate a
all other bus cycles.
allowing access to 8-, 16-, and 32-bit data ports through the use of asyn-
chronous cycles controlled by DSACK0 and DSACK1. It also supports syn-
misaligned transfers may require additional bus cycles, regardless of port
size.
burst request (CBREQ) signal to attempt to fill four entries within a line in
one ofthe on-chip caches. This mode is compatible with nibble, static column,
or page mode dynamic RAMs. The burst fill operation uses synchronous bus
cycles, each terminated by STERM, to fetch as many as four long words.
The MC68030 dynamically interprets the port size of the addressed device
during each bus cycle, allowing operand transfers to or from 8-, 16-, and 32-
bit ports. During an asynchronous operand transfer cycle, the slave device
mination signal (STERM) as part of the bus protocol. During a read cycle,
cycle, it indicates that the external device has successfully stored the data.
In either case, it terminates the cycle and indicates that the transfer was made
be used in the absence of DSACKx or STERM to indicate a bus error condition.
It can also be asserted in conjunction with DSACKx or STERM to indicate a
bus error condition, provided it meets the appropriate timing described in
retry termination. Again, the BERR and HALT signals can be asserted simul-
For synchronous bus cycles, external devices assert the synchronous ter-
MC68030 USER'S MANUAL
MOTOROLA