MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 169

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7
7-8
erands for the definition of misaligned operand. The data multiplexer
establishes the necessary connections for different combinations of address
The multiplexer takes the four bytes of the 32-bit bus and routes them to
their required positions. For example, OP0 can be routed to D24-D31, as
would be the normal case, or it can be routed to any other byte position to
support a misaligned transfer. The same is true for any of the operand bytes.
The positioning of bytes is determined by the size (SIZ0 and SIZ1) and address
The SIZ0 and SIZ1 outputs indicate the remaining number of bytes to be
transferred during the current bus cycle, as shown in Table 7-2.
The number of bytes transferred during a write or noncachable read bus
first bus cycle of a long-word transfer to a word port, the size outputs indicate
that four bytes are to be transferred, although only two bytes are moved on
that bus cycle. Cachable read cycles must always transfer the number of
bus for 8-, 16-, and 32-bit devices. The four bytes shown in Figure 7-4 are
connected through the internal data bus and data multiplexer to the external
data bus. This path is the means through which the MC68030 supports dy-
namic bus sizing and operand misalignment. Refer to 7.2.2 Misaligned Op-
and data sizes.
(A0 and A1) outputs.
cycle is equal to or less than the size indicated by the SIZ0 and SIZ1 outputs,
depending on port width and operand alignment. For example, during the
A0 and A1 also affect operation of the data multiplexer. During an operand
transfer, A2-A31 indicate the long-word base address of that portion of the
operand to be accessed; A0 and A1 indicate the byte offset from the base.
Table 7-3 shows the encodings of A0 and A1 and the corresponding byte
offsets from the long-word base.
Figure 7-4 shows the required organization of data ports on the MC68030
bytes indicated by the port size.
LONG WORD OPERAND
Figure 7-3. Internal Operand Representation
MC68030 USER'S MANUAL
I
OPO
WORD OPERANO
I
0PI
[
I
BYTE OPEBAND
OP2
OP2
1
L
}
7
OP3
0P3
OP3
MOTOROLA