MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 438

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
[cAIPcI°RI
When the main processor receives this primitive, it reads a control register
After reading a valid code from the register select CIR, if D R = 0 , the main
to the
f r o m the operand CIR and places it in the specified control register.
select code from the register select CIR. This code determines which main
processor control register is transferred. Table 10-5 lists the valid control
VIOLATIONS).
register select codes. If the control register select code is not valid, the MC68030
initiates protocol violation exception processing (refer to 10.5.2.1 PROTOCOL
processor writes the long-word operand from the specified control register
Figure 10-34. Transfer Main Processor Control Register Primitive Format
15
14
operand
13
CJR. If DR = 1, the main processor reads a long-word
t2
° I 1 I I I 0 I' I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0
i
All other codes cause a protocol violation exception
Table 10-5. Main Processor Control
11
x000
x001
xO02
x800
x801
x802
x803
x804
Hex
MC68030 USER'S MANUAL
10
Register Selector Codes
Source Function Code (SFC) Register
Destination Function Code (DFC) Register
User Stack Pointer (USP)
Vector Base Register (VBR)
Cache Address Register (CAAR)
Master Stack Pointer (MSP)
Interrupt Stack Pointer (ISP)
Cache Control Register (CACR)
9
8
Control Register
7
6
5
4
3
2
operand
1
10-51
0
I
10