MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 231

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.4.1.1 INTERRUPT ACKNOWLEDGE C Y C L E - - TERMINATED NORMALLY.
7-70
the interrupt vectors for the routines they use. The following paragraphs
The interrupt acknowledge cycle is a read cycle. It differs from the asyn-
The responding device places the vector number on the data bus during the
with either STERM or DSACKx. Figure 7-43 is the flowchart of the interrupt
the MC68030 processes an interrupt exception, it performs an interrupt ac-
knowledge cycle to obtain the number of the vector that contains the starting
Some interrupting devices have programmable vector registers that contain
describe the interrupt acknowledge cycle for these devices. Other interrupting
conditions or devices cannot supply a vector number and use the autovector
cycle described in 7.4.1.2 AUTOVECTOR INTERRUPT
chronous read cycle described in 7.3.1 Asynchronous Read Cycle o r t h e syn-
chronous read cycle described in 7.3.4 Synchronous Read Cycle in that it
accesses the CPU address space. Specifically, the differences are:
interrupt acknowledge cycle. Beyond this, the cycle is terminated normally
acknowledge cycle.
location of the interrupt service routine.
3. The CPU space type field (A16-A19) is set to $F, the interrupt acknowl-
4. A20-A31, A4-A15, and A0 are set to one.
2. A1, A2, and A3 are set to the interrupt request level (the inverted values
1. FC0-FC2 are set to seven (FC0/FC1/FC2 = 111) for CPU address space.
of IPL0, IPL1, and IPL2, respectively).
edge code.
MC68030 USER'S MANUAL
ACKNOWLEDGE CYCLE.
MOTOROLA
When