MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 561
MC68030CRC33C
Manufacturer Part Number
MC68030CRC33C
Description
IC MPU 32BIT ENHANCED 128-PGA
Manufacturer
Freescale Semiconductor
Specifications of MC68030CRC33C
Processor Type
M680x0 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
128-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
33MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
128
Package Type
PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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12-36
12.7.1 STATUS and REFILL
As shown in Table 12-4, the number of consecutive clocks during which
The REFILL signal identifies when the microsequencer requests an instruction
The MC68030 provides the STATUS and REFILL signals to identify internal
controller, information concerning the processing state of the microsequen-
cer is not available by monitoring bus signals by themselves. The internal
and instruction pipeline refills. STATUS and REFILL track only the internal
microsequencer activity and are not directly related to bus activity.
STATUS is asserted indicates an instruction boundary, an exception to be
processed, or that the processor has halted. Note that the processor halted
condition is an internal error state in which the microsequencer has shut
itself down due to a double bus fault and is not related to the external
assertion of the HALT input signal. The HALT signal only affects bus oper-
ation, not the microsequencer.
struction execution to handle nonsequential events. Both exceptions and
include branches, jumps, instruction traps, returns, coprocessor general in-
microsequencer activity associated with the processing of data in the pipe-
line. Since bus cycles are independently controlled and scheduled by the bus
activity identified by the STATUS and REFILL signals include instruction
boundaries, some exception conditions, when the microsequencer has halted,
pipeline refill. Refill requests are a result of having to break sequential in-
instructions can cause the assertion of REFILL. Instructions that cause refills
2 Clocks
3 Clocks
1 Clock
.Continuously
Asserted for
T a b l e 12-4. M i c r o s e q u e n c e r S T A T U S I n d i c a t i o n s
Sequencer at instruction boundary will begin execution of next instruction
Sequencer at instruction boundary but will not begin next instruction immediately
due to:
MMU address translation cache miss -- processor to begin table search
Exception processing to begin for:
Processor halted due to double bus fault
• pending interrupt exception
• reset OR
• bus error OR
• address error OR
• pending trace exception
• spurious interrupt OR
• autovectored interrupt OR
•
F-line instruction (no coprocessor responded)
OR
OR
MC68030 USER'S MANUAL
Indicates
MOTOROLA
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