MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 284

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
LEVEL 6 EXAMPLE:
LEVEL 7 EXAMPLE:
I
I
I
J
I
L
to the assertion of an interrupt level on the IPL lines. IPEND signals to external
interrupt request level of 7. The only difference between mask values of 6
and 7 occurs when the interrupt request level is 7 and the mask value is 7.
The MC68030 asserts the interrupt pending signal (IPEND) when it makes an
devices that an interrupt exception will be taken at an upcoming instruction
Note that a mask value of 6 and a mask value of 7 both inhibit request levels
1-6 from being recognized. In addition, neither masks a transition to an
If the mask value is lowered to 6, a second level 7 interrupt is recognized.
interrupt request pending. Figure 8-4 shows the assertion of IPEND relative
boundary (following any higher priority exception).
IF
~E
IF
IF STILL
IF
IF
IF
IF STILL
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EXTERNAL IPL2 :IPLO
001 (S0)
001 ($6)
oo] ($6)
000 ($7)
000 ($7)
000 ($7)
too ~$3)
100 ($3)
TO0 ($3)
100 ($31
Figure 8-3. Interrupt Recognition Examples
THEN
AND STILL
AND STILL
AND RTE SO THAT
THEN
AND STILL
AND STILL
AND RTE SO THAT
M068030 USER'S MANUAL
÷
{
SR ,",;ASK (12:10)
II0
?10 188)
101 ($5)
101 (S5)
,10 ($6)
101 ($5)
111 ($7)
111 ($7)
111 ($7)
101 ($5)
($6)
~
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AND
THEN
THEN
THEN
AND
THEN
THEN
THEN
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INITIAL CONDITIONS
INITIAL CONDITIONS
NO ACTION
LEVEL 6 INTERRUPT
NO ACTION
LEVEL 6 INTERRUPT
LEVEL 7 INTERRUPT
NO ACTION
LEVEL 7 INTERRUPT
LEVEL 7 INTERRUPT
ACTION
I
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J
J
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(TRANSITION)
(LEVEL COMPARISON)
LEVEL COMPARISON)
LEVEL COMPARISON)
TRANSITION)
8-17
8