MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 300

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

M O T O R O L A
SP
SP+s02-"
SP+$02~
+S08
+SOC
+$12
+$08 I
+S02
+S06
+son I0 0 0 0 I
+S02
+
+
S 0 6 [
COPROCESSOR MID-INSTRUCTION STACK FRAME (10 WORDS) - FORMAT SO
~
15
15
~5
1 0 0
0 0 0
0
THROWAWAY FOUR WORD STACK FRAME - FORMAT $1
O
FOUR WOO0 STACK FRAME - FORMAT $0
1 O I
SIX WORB STACK FRAME - FORMAT $2
I I
I
I
11
Table 8-6. Exception Stack Frames (Sheet 1 of 2)
Stack Frames
INSTRUCTION ADORESS
INSTRUCTION ADDRESS -
INTERNAL OEGtSTERSr
PROGRAM COUNTER
PROGRAM COUNTER
PROGRAM COUNTER
PROGRAM COUNTER
STATUS REGISTER
$T~IIS RE(E]LR
STATUS REGISTER
STATUS REGISTER
4 WOROS
VECTOR OFFSET
VECTOR OFFSET
VECTOR OFFSET
VECTOR OFFSET
M C 6 8 0 3 0 U S E R ' S M A N U A L
-
0
• Coprocessor
• Main-Detected
• Interrupt Detected
• CHK
• CHK2
• cpTRAPcc
• TRAPcc
• TRAPV
• Trace
• Zero Divide
• MMU Configuration
• Coprocessor Post-Instruction
• Interrupt
• Format Error
• TRAP =N
• II!ega! Instruction [illegal instruction]
• A-Line
• F-Line instruction iF-line instruction]
• Privilege Violation ]First word of instruction causing
• Created on Interrupt Stack
Coprocessor
with 'null come again
with interrupts
from master state to
Midqnstruction
Protocol Violation
During Coprocessor
Instruction (supported
allowed' primitive)
Pre-lnstruction
during interrupt exception
processing when transition
interrupt state occurs
Exception Types (Stacked PC Points to)
Instruction [A-line
[Next instruction]
[RTE or cpRESTORE instruction]
[Next instruction]
TOp-Word of instruction that
Privilege Violation]
returned the Take Pre-/nstruction
primitive]
[Next instruction for all these
[Next word to be fetched
INSTRUCTION ADDRESS
INSTRUCTION ADDRESS
instructionJ
from instruction stream
for all these exceptionsl
exceptions]
is the
instruction that caused the
exception
instruction that caused
the exception
is the address of the
[Next instruction--same
as on master stack]
address
of the
8-33
8