MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 402

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

10.2.2.1.2 Protocol.
10.2.2.2 SET ON COPROCESSOR CONDITION INSTRUCTION.
10.2.2.2.1 Format.
MOTOROLA
c a l c u l a t i o n .
instructions. The main processor initiates the instruction by writing the
to the coprocessor. The main processor then reads the response CIR to de-
termine its next action. The coprocessor can return a response primitive to
turns the false condition indicator, the main processor executes the next
the main processor to execute. The scanPC must be pointing to the location
F-line operation word to the condition CIR to transfer the condition selector
dition indicator, the processor adds the displacement to the MC68030 scanPC
the 16-bit displacement to a long-word value for the destination address
cessor condition instructions set or reset a flag (a data alterable byte) ac-
cording to a condition evaluated by the coprocessor. The operation of this
flags that control program flow.
request services necessary to evaluate the condition. If the coprocessor re-
instruction in the instruction stream. If the coprocessor returns the true con-
(refer to 10.4.1 ScanPC) to determine the address of the next instruction for
of the first word of the displacement in the instruction stream when the
address is calculated. The displacement is a twos-complement integer that
can be either a 16-bit word or a 32-bit long word. The processor sign-extends
instruction is similar to the operation of the Scc instruction in the M68000
Family instruction set. Although the Scc instruction and the cpScc instruction
do not explicitly cause a change of program flow, they are often used to set
dition instruction, denoted by the cpScc mnemonic.
15
14
13
Figure 10-11. Set On Coprocessor Condition (cpScc)
Figure 10-11 shows the format of the set on coprocessor con-
Figure 10-8 shows the protocol for the cpBcc.L and cpBcc.W
12
OPTIONAL EFFECTIVE ADDRESS EXTENSION WORDS (0-5 WORDS)
OPTIONAL COPROCESSOR-DEFI N ED EXTENSION WORDS
11
MC68030 USER'S MANUAL
9
8
7
6 5
CONDITION SELECTOR
EFFECTI V E ADDRESS
The set on copro-
10-15
0
1C