MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 528

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
1 2 . 1 . 2 H a r d w a r e
feature must be checked. Because of the MC68030 cache organization and
or data access the user should either designate that area of memory as
cycles from multibyte ports.
The HAL] = input-only signal of the MC68030 is slightly different than the
When used in a system originally designed for both an MC68020 and an
with a jumpered header). However, if left in the system, the MC68851 is not
the MC68030's MMUDIS signal is asserted. The benefit in removing the
implementation, cachable read bus cycles are expected to transfer the entire
port width of data (as indicated by the DSACKx encoding), regardless of how
not supply the amount of data required by the MC68030. If the target system
does not supply the full port width with valid data for any cachable instruction
noncachable (with the MMU) or not enable the corresponding on-chip cache(s).
option; frequently, the byte select logic is generated by a single PAL, which
might easily be replaced or reprogrammed to select all bytes during read
bidirectional HALT signal of the MC68020. However, this should not cause
any problems beyond eliminating an indication to the external system (e.g.,
lighting an LED) that the processor has halted due to a double bus fault.
MC68851, the MC68851 may be left in the system or removed (and replaced
accessible to the programmer with the M68000 coprocessor interface. All
MC68851 is that the minimum asynchronous bus cycle time to the physical
bus is reduced from four clock cycles to three.
RMC, LBRO, LBG, LBGACK, and LBGI. During translation table searches, the
MC68851 asserts the cache load inhibit (CLI) signal but not RMC; whereas,
Before enabling the on-chip caches of the MC68030, an important system
many bytes are actually requested by the SIZx pins. The MC68020 did not
have this requirement, and system memory banks or peripherals may or may
In some systems, modifying the target system hardware may also be an
MMU instructions access the MC68030's on-chip MMU. This is true even if
If the MC68851 is removed and replaced with a jumpered header, the fol-
lowing MC68851 signals may need special system-specific consideration: CLI,
D i f f e r e n c e s
MC68030 USER'S MANUAL
12-3