MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 431

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

IO
10-44
four bytes are valid; all other lengths (zero, for example) cause the main
The length of 0-255 bytes does not apply to an immediate operand. The
When the main processor receives this primitive during the execution of a
the instruction operation word is in the category specified by the primitive.
transfers the number of bytes specified in the primitive between the operand
for transfers involving the operand CIR.
transfer from the effective address to the operand CIR, and DR = 1 specifies
the instruction operation word match, the MC68030 initiates protocol viola-
tion exception processing if the primitive requests a write to a nonalterable
effective address.
The length in bytes of the operand to be transferred is specified by bits [0-7]
of the primitive format. Several restrictions apply to operand lengths for
certain effective addressing modes. If the effective address is a main pro-
cessor register (register direct mode), only operand lengths of one, two, or
processor to initiate protocol violation exception processing. Operand lengths
of 0-255 bytes are valid for the memory addressing modes.
length of an immediate operand must be one byte or an even number of
otherwise, the main processor initiates protocol violation exception pro-
cessing.
general category instruction, it verifies that the effective address encoded in
effective address extension words at the current scanPC address and incre-
ments the scanPC by two for each word referenced. The main processor then
CIR and the effective address using long-word transfers whenever possible.
The DR bit specifies the direction of the operand transfer. DR=0 requests a
Even when the valid effective address fields specified in the primitive and in
bytes (less than 256), and the direction of transfer must be to the coprocessor;
If so, the processor calculates the effective address using the appropriate
Refer to 10.3.80perand CIR for information concerning operand alignment
a transfer from the operand CIR to the effective address.
MC68030 USER'S MANUAL
MOTOROLA