MC68LC060RC66 Freescale Semiconductor, MC68LC060RC66 Datasheet
MC68LC060RC66
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MC68LC060RC66 Summary of contents
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M68060 User’s Manual Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability ...
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Documentation Comments FAX 512-891-8593—Documentation Comments Only The Motorola High-End Technical Publications Department provides a fax number for you to submit any questions or comments about this document or how to order other documents. We welcome your suggestions for improving our ...
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Field Applications Engineering Available Through All Sales Offices UNITED STATES ALABAMA , Huntsville ARIZONA , Tempe CALIFORNIA , Agoura Hills CALIFORNIA , Los Angeles CALIFORNIA , Irvine CALIFORNIA , Rosevllle CALIFORNIA , San Diego CALIFORNIA , Sunnyvale COLORADO , Colorado ...
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The complete documentation package for the MC68060, MC68LC060, and MC68EC060 (collectively called M68060) consists of the M68060UM/AD, M68060 User’s Manual , and the M68000PM/AD, M68000 Family Programmer’s Reference Manual . The M68060 User’s Manual describes the capabilities, operation, and programming ...
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MC68060 ACRONYM LIST AGU—address generation unit ALU—arithmetic logic unit ATC—address translation cache BUSCR—bus control register CACR—cache control register CCR—condition code register CM—cache mode CPU—central processing unit DFC—destination function code DTTx—data transparent translation register DRAM—dynamic random access memory FPIAR—floating-point instruction address ...
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MC68060 Acronym List MMUSR—memory management unit status register M68060SP—M68060 software package NANs—not-a-numbers NOP—no operation OEP—operand execution pipeline OPU—operand pipe unit PC—program counter PCR—processor configuration register PGI—page index field PI—pointer index field PLL—phase-locked loop pOEP—primary operand execution pipeline RI—root index field ...
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TABLE OF CONTENTS 1.1 Differences Among M68060 Family Members.............................................. 1-3 1.1.1 MC68LC060................................................................................................ 1-3 1.1.2 MC68EC060 ............................................................................................... 1-3 1.1.2.1 Address Translation Differences .............................................................. 1-3 1.1.2.2 Instruction Differences .............................................................................. 1-3 1.2 Features........................................................................................................ 1-4 1.3 Architecture................................................................................................... 1-4 1.4 Processor Overview...................................................................................... 1-5 1.4.1 Functional ...
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Table of Contents 2.3.6 Transfer Size (SIZ1, SIZ0).......................................................................... 2-6 2.3.7 Bus Lock (LOCK)........................................................................................ 2-6 2.3.8 Bus Lock End (LOCKE).............................................................................. 2-6 2.3.9 Cache Inhibit Out (CIOUT) ......................................................................... 2-7 2.3.10 Byte Select Lines (BS3–BS0)..................................................................... 2-7 2.4 Master Transfer Control Signals ................................................................... 2-7 ...
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Integer Unit Execution Pipelines ................................................................... 3-1 3.2 Integer Unit Register Description .................................................................. 3-2 3.2.1 Integer Unit User Programming Model ....................................................... 3-2 3.2.1.1 Data Registers (D7–D0) ........................................................................... 3-2 3.2.1.2 Address Registers (A6–A0) ...................................................................... 3-2 3.2.1.3 User Stack Pointer (A7) ............................................................................ ...
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Table of Contents 4.6.2 Effect of MDIS on Address Translation .................................................... 4-30 4.7 MMU Instructions........................................................................................ 4-30 4.7.1 MOVEC .................................................................................................... 4-30 4.7.2 PFLUSH ................................................................................................... 4-30 4.7.3 PLPA ........................................................................................................ 4-30 5.1 Cache Operation........................................................................................... 5-1 5.2 Cache Control Register ................................................................................ 5-5 5.3 Cache ...
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Accrued Exception Byte ........................................................................... 6-6 6.1.4 Floating-Point Instruction Address Register (FPIAR) ................................. 6-7 6.2 Floating-Point Data Formats and Data Types............................................... 6-7 6.3 Computational Accuracy ............................................................................. 6-11 6.3.1 Intermediate Result................................................................................... 6-12 6.3.2 Rounding the Result ................................................................................. 6-13 6.4 Postprocessing Operation........................................................................... ...
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Table of Contents 7.7 Processor Data Transfers........................................................................... 7-12 7.7.1 Byte, Word, and Long-Word Read Transfer Cycles ................................. 7-12 7.7.2 Line Read Transfer................................................................................... 7-15 7.7.3 Byte, Word, and Long-Word Write Cycles................................................ 7-20 7.7.4 Line Write Cycles..................................................................................... 7-25 7.7.5 Locked Read-Modify-Write Cycles ...
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Exception Priorities ..................................................................................... 8-17 8.4 Return from Exceptions .............................................................................. 8-19 8.4.1 Four-Word Stack Frame (Format $0) ....................................................... 8-19 8.4.2 Six-Word Stack Frame (Format $2) .......................................................... 8-20 8.4.3 Floating-Point Post-Instruction Stack Frame (Format $3) ........................ 8-20 8.4.4 Eight-Word Stack Frame ...
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Table of Contents 10.1.3 Dispatch Test 3: Allowable Effective Addressing Mode in the sOEP ....... 10-8 10.1.4 Dispatch Test 4: Allowable Operand Data Memory Reference ................ 10-8 10.1.5 Dispatch Test 5: No Register Conflicts on sOEP.AGU Resources .......... 10-8 10.1.6 ...
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Other Considerations................................................................................ 11-6 11.2 Using an MC68060 in an Existing MC68040 System ................................. 11-6 11.2.1 Power Considerations............................................................................... 11-6 11.2.1 Voltage Conversion ................................................................ 11-6 11.2.1.1.1 Linear Voltage Regulator Solution........................................................ 11-7 11.2.1.1.2 Switching Regulator Solution................................................................ 11-7 11.2.1.2 Input ...
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Table of Contents C.1 Module Format..............................................................................................C-2 C.2 Unimplemented Integer Instructions .............................................................C-4 C.2.1 Integer Emulation Results ..........................................................................C-5 C.2.2 Module 1: Unimplemented Integer Instruction Exception (MC68060ISP)............................................................................................C-5 C.2.2.1 Unimplemented Integer Instruction Exception Module Entry Points ........C-6 C.2.2.2 Unimplemented Integer Instruction Exception Module Call-Outs ...
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LIST OF ILLUSTRATIONS 1-1 MC68060 Block Diagram ................................................................................... 1-6 1-2 Programming Model ......................................................................................... 1-12 2-1 Functional Signal Groups ................................................................................... 2-3 3-1 MC68060 Integer Unit Pipeline .......................................................................... 3-1 3-2 Integer Unit User Programming Model............................................................... 3-2 3-3 Integer Unit Supervisor Programming Model ...
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List of Illustrations 6-4 Floating-Point Condition Code (FPSR) .............................................................. 6-5 6-5 Floating-Point Quotient Byte (FPSR) ................................................................. 6-5 6-6 Floating-Point Exception Status Byte (FPSR).................................................... 6-6 6-7 Floating-Point Accrued Exception Byte (FPSR)................................................. 6-6 6-8 Intermediate Result Format.............................................................................. 6-12 6-9 Rounding Algorithm Flowchart ...
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Line Read Access Bus Cycle Terminated with TEA Timing............................. 7-49 7-39 Retry Read Bus Cycle Timing .......................................................................... 7-50 7-40 Line Write Retry Bus Cycle Timing................................................................... 7-51 7-41 MC68040-Arbitration Protocol State Diagram .................................................. 7-57 7-42 MC68060-Arbitration Protocol State Diagram .................................................. ...
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List of Illustrations 12-12 Clock Input Timing Diagram............................................................................. 12-3 12-13 Drive Levels and Test Points for AC Specifications ......................................... 12-7 12-14 Reset Configuration Timing.............................................................................. 12-8 12-15 Read/Write Timing ........................................................................................... 12-9 12-16 Bus Arbitration Timing.................................................................................... 12-10 12-17 Bus Arbitration Timing (Continued) ...
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Data Formats.................................................................................................... 1-14 1-2 Effective Addressing Modes............................................................................. 1-15 1-3 Instruction Set Summary .................................................................................. 1-16 1-4 Notational Conventions .................................................................................... 1-21 2-1 Signal Index........................................................................................................ 2-1 2-2 Transfer-Type Encoding..................................................................................... 2-4 2-3 Normal and MOVE16 Access TMx Encoding..................................................... 2-5 2-4 Alternate Access TMx ...
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List of Tables 7-7 MC68040-Arbitration Protocol State Description ............................................. 7-56 7-8 MC68060-Arbitration Protocol State Transition Conditions.............................. 7-62 7-9 MC68060-Arbitration Protocol State Description ............................................. 7-63 7-10 Special Mode vs. IPLx Signals......................................................................... 7-74 8-1 Exception Vector Assignments .......................................................................... 8-4 8-2 Interrupt Levels ...
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C-4 Unimplemented Data Formats and Data Types .............................................. C-13 C-5 UNIX Operating System Calls ......................................................................... C-23 C-6 Instructions Not Handled by the M68060SP ................................................... C-26 C-7 Files Provided in an M68060SP Release........................................................ C-27 D-1 M68000 Family Instruction Set and Processor ...
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List of Tables xxvi M68060 USER’S MANUAL MOTOROLA ...
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SECTION 1 INTRODUCTION The superscalar MC68060 represents a new line of Motorola microprocessor products. The first generation of the M68060 product line consists of the MC68060, MC68LC060, and MC68EC060. All three microprocessors offer superscalar integer performance of over 100 MIPS ...
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Introduction unit and the operand execution units. Fixed format instructions are dispatched to dual four- stage pipelined RISC operand execution engines where they are then executed. The branch cache also plays a major role in achieving the high performance levels ...
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DIFFERENCES AMONG M68060 FAMILY MEMBERS Because the functionality of individual M68060 family members are similar, this manual is organized so that the reader will take the following differences into account while reading the rest of this manual. Unless otherwise ...
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Introduction translated. The PLPA instruction can only generate an access error exception only on super- visor or write protection violation cases. The PFLUSH instruction operates as a virtual NOP instruction. When the MOVEC instruction is used to access the SRP ...
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Architectural highlights of the MC68060 include: • Four-Stage Instruction Fetch Unit (IFU) — 64-Entry Instruction Address Translation Cache (ATC), Organized as 4-Way Set- Associative, for Fast Virtual-to-Physical Address Translations — 8- Kbyte, 4-Way Set-Associative, Physically-Mapped Instruction Cache —256-Entry, 4-Way Set-Associative, ...
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Introduction The architecture of the MC68060 processor is implemented in the following major blocks: • Execution Unit —Instruction Fetch Unit —Integer Unit —FPU • Memory Units —Instruction Memory Unit • Instruction ATC • Instruction Cache • Instruction Cache Controller —Data ...
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The integer unit implements a subset of the MC68040 instruction set. The FPU implements a subset of the MC68881/2 coprocessor instruction set. The instruction and data memory units manage the ATCs and the instruction and data caches. The ATCs provide ...
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Introduction 1.4.2.2 INTEGER UNIT. The integer unit contains dual integer execution pipelines, inter- face logic to the FPU, and control logic for data written to the data cache and MMU. The superscalar design of the dual integer execution pipelines provide ...
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The MC68060 is compatible with the ANSI/IEEE Standard 754 for Binary Floating-Point Arithmetic . The MC68060’s FPU has been optimized to execute the most commonly used subset of the MC68881/MC68882 instruction sets. Software emulates floating-point instruc- tions not directly supported ...
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Introduction cute concurrently while the processor is performing an external access for a previous instruction. Each MC68060 cache is 8 Kbytes, accessed by physical addresses. The data cache can be configured as write-through or deferred copyback on a page basis. ...
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The processor halts when it receives an access error or generates an address error while in the exception processing state. For example, if during exception processing of one access error another access error occurs, the MC68060 is unable to complete ...
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Introduction modifying the S-bit of the SR. After these instructions execute, the instruction pipeline is flushed and is refilled from the appropriate address space. The MC68060 integrates the functions of the integer unit, FPU, and MMU. The registers depicted in ...
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M68000 family architecture allows for the writing of application soft- ware that executes in the user mode and migrates to the MC68060 from any M68000 family platform without modification. The supervisor programming model contains the control ...
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Introduction byte. A floating-point exception handler can use the address in the 32-bit floating-point instruction address register (FPIAR) to locate the floating-point instruction that has caused an exception. Instructions that do not modify the FPIAR can be used to read ...
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An instruction’s addressing mode can specify the value of an operand, a register containing the operand, or how to derive the effective address of an operand in memory. Each address- ing mode has an assembler syntax. Some instructions imply the ...
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Introduction Table 1-3. Instruction Set Summary Opcode ABCD BCD Source + BCD Destination + X ˘ Destination ADD Source + Destination ˘ Destination ADDA Source + Destination ˘ Destination ADDI Immediate Data + Destination ˘ Destination ADDQ Immediate Data + ...
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Table 1-3. Instruction Set Summary (Continued) Opcode CLR 0 ˘ Destination CMP Destination – Source ˘ cc CMPA Destination – Source CMPI Destination – Immediate Data CMPM Destination – Source ˘ cc Compare Rn < > UB ...
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Introduction Table 1-3. Instruction Set Summary (Continued) Opcode FINT Floating-Point Integer Part FINTRZ Floating-Point Integer Part, Round-to-Zero Source ˘ Destination FMOVE Source ˘ Destination FMOVE Register List ˘ Destination 9 FMOVEM Source ˘ Register List Register List ˘ Destination 9 ...
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Table 1-3. Instruction Set Summary (Continued) Opcode SP – 4 ˘ SP; PC ˘ (SP) JSR Destination Address ˘ PC LEA <ea> ˘ – 4 ˘ SP; An ˘ (SP) LINK SP ˘ An, SP+d ˘ ...
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Introduction Table 1-3. Instruction Set Summary (Continued) Opcode If supervisor state ORI to SR then Source V SR ˘ SR else TRAP Source (Unpacked BCD) + adjustment ˘ PACK Destination (Packed BCD) PEA SP – 4 ˘ SP; <ea> ˘ ...
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Table 1-3. Instruction Set Summary (Continued) Opcode NOTES: 1.Where d is direction, left or right. 2.Emulation support only, not supported in hardware. 3.Where r is rounding precision, single or double precision. 4.List refers to register. 5.List refers to control registers ...
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Introduction Table 1-4. Notational Conventions (Continued) Rn Any Address or Data Register Rx, Ry Any source and destination registers, respectively. Xn Index Register—An, Dn, or suppressed. + inf Positive Infinity Operand Data Format: Byte (B), Word (W), Long (L), Single ...
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SECTION 2 SIGNAL DESCRIPTION This section contains brief descriptions of the MC68060 signals in their functional groups (see Figure 2-1). Each signal’s function is briefly explained, referencing other sections con- taining detailed information about the signal and related operations. Table ...
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Signal Description Table 2-1. Signal Index (Continued) Signal Name Mnemonic Transfer Retry Acknowl- TRA edge Transfer Error Acknowl- TEA edge Transfer Cycle Burst In- TBI hibit Transfer Cache Inhibit TCI Snoop Control SNOOP Bus Request BR Bus Grant BG Bus ...
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A31–A0 ADDRESS BUS AND CONTROL D31–D0 DATA BUS TRANSFER ATTRIBUTES MASTER TRANSFER CONTROL SLAVE TRANSFER CONTROL Figure 2-1. Functional Signal Groups 2.1 ADDRESS AND CONTROL SIGNALS The following paragraphs describe the MC68060 address and control signals. 2.1.1 Address Bus (A31–A0) ...
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Signal Description nals are examined to determine whether the processor should invalidate matching cache entries to maintain cache coherency. 2.1.2 Cycle Long-Word Address (CLA) This active-low input signal controls the operation of A3 and A2 during bus cycles. Following each ...
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TMx signals are negated. When the MC68060 is not the bus master, the TMx signals are in a high-impedance state. MOTOROLA M68060 USER’S MANUAL Signal Description 2-5 ...
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Signal Description Table 2-3. Normal and MOVE16 Access TMx Encoding TM2 *MOVE16 accesses use only these encodings. Table 2-4. Alternate Access TMx Encoding TM2 ...
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MC68060 invokes default transparent translation. The cache mode, user page attributes, and other TTR fields for the default translation are defined by the contents of the TCR. For more information about the UPAx signals, refer to Section 4 ...
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Signal Description for one full BCLK cycle and then three-stated one BCLK cycle after the address bus is idled. If LOCKE was already negated in the BCLK cycle in which the MC68060 relinquishes the bus, it will be three-stated in ...
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Transfer Start (TS) The processor asserts this three-state bidirectional signal for one clock-enabled clock period to indicate the start of each bus cycle. During alternate bus master accesses, the processor monitors TS and SNOOP to detect the start of ...
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Signal Description to rerun the current bus cycle. The assertion of TRA on any transfer other than the first trans- fer is ignored. The assertion of TRA has precedence over TA, but does not have precedence over TEA. If the ...
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ARBITRATION SIGNALS The following control signals support bus mastership control by an external arbiter over the MC68060. Refer to Section 7 Bus Operation for detailed information about the relationship of the arbitration signals to bus operation. 2.7.1 Bus Request ...
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Signal Description The MC68060 provides the BB signal and protocol to provide compatibility with MC68040- style buses. Either the BTT signal and protocol or the BB signal and protocol (but not both) should be used. The unused signal, either BTT ...
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MMU Disable (MDIS) When asserted, this input signal dynamically disables the MC68060 internal operand data and instruction MMUs on the next internal access boundary. While MDIS is asserted, all accesses bypass the MMU ATCs, and thus translate transparently. The ...
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Signal Description nal peripheral devices. Refer to Section 7 Bus Operation for bus information related to interrupts and to Section 8 Exception Processing for interrupt information. 2.9.3 Autovector (AVEC) This input signal is asserted with TA during an interrupt acknowledge ...
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Hex PST4 PST3 PST2 $ $ $ $ $ $ $ $ $ ...
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Signal Description state on the rising edge of CLK regardless of the state of the CLKEN) only on those rising edges of CLK which are spanned by the assertion of CLKEN. CLKEN may be used to allow the external bus ...
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Test Data In (TDI) This input signal provides a serial data input to the TAP. TDI should be tied to V used and emulation mode is not to be used. 2.11.5 Test Data Out (TDO) This three-state output signal ...
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Signal Description Signal Name Address Bus Cycle Long-Word Address Data Bus Transfer Type 1 Transfer Type 0 Transfer Modifier Transfer Line Number User-Programmable Attributes Read/Write Transfer Size Bus Lock Bus Lock End Cache Inhibit Out Byte Select Transfer Start Transfer ...
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SECTION 3 INTEGER UNIT This section describes the organization of the MC68060 integer unit and presents a brief description of the associated registers. Refer to Section 4 Memory Management Unit for details concerning the paged memory management unit (MMU) programming ...
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Integer Unit The operation of the instruction fetch unit (IFU) and the OEPs are decoupled by a 96-byte FIFO instruction buffer. The IFU prefetches instructions every processor clock cycle, stop- ping only if the instruction buffer is full or encountering ...
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When the S-bit in the status register (SR) is clear, the USP is the active stack pointer. A subroutine call saves the program counter (PC) on the active system stack, and ...
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Integer Unit The supervisor programming model consists of the registers available to the user as well as the following control registers: • 32-Bit Supervisor Stack Pointer (SSP, A7) • 16-Bit Status Register (SR) • 32-Bit Vector Base Register (VBR) • ...
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ALTERNATE FUNCTION CODE REGISTERS. The alternate function code regis- ters contain 3-bit function codes. Function codes can be considered extensions of the 32-bit logical address that optionally provides as many as eight 4-Gbyte address spaces. The pro- cessor automatically ...
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SECTION 4 MEMORY MANAGEMENT UNIT This section does not apply to the MC68EC060. Refer to Appendix B MC68EC060 for details. The MC68060 supports a demand-paged virtual memory environment. Demand means that programs request permission to use memory area by accessing ...
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Memory Management Unit Figure 4-1 illustrates the MMUs contained in the two memory units, one for instructions (sup- porting instruction prefetches) and one for data (supporting all other accesses). Each MMU contains a 64-entry ATC, two transparent translation registers (TTRs), ...
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MEMORY MANAGEMENT PROGRAMMING MODEL The memory management programming model is part of the supervisor programming model for the MC68060. The seven registers that control and provide status information for address translation in the MC68060 are: the user root pointer ...
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Memory Management Unit 4.1.2 Translation Control Register The 32-bit TCR contains control bits which select translation properties. The operating sys- tem must flush the ATCs before enabling address translation since the TCR accesses and reset do not flush the ATCs. ...
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FITC—1/2-Cache Mode (Instruction ATC The instruction ATC operates with 64 entries The instruction ATC operates with 32 entries. DCO—Default Cache Mode (Data Cache Writethrough, cachable 01 = Copyback, cachable 10 = Cache-inhibited, precise exception ...
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Memory Management Unit 4.1.3 Transparent Translation Registers The data transparent translation registers (DTTR0 and DTTR1) and instruction transparent translation registers (ITTR0 and ITTR1) are 32-bit registers that define blocks of logical address space that are untranslated by the MMU (the ...
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These bits can be programmed by the user to support external address- ing, bus snooping, or other applications. CM—Cache Mode This field selects the cache mode and access precision as follows Cachable, Writethrough 01 = ...
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Memory Management Unit ROOT POINTER Figure 4-6. Translation Table Structure descriptor, can be used when two or more logical addresses access a single page descrip- tor. The table search uses logical addresses to access the translation tables. Figure 4-7 illus- ...
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For 8-Kbyte pages, the five bits of the PGI field are multiplied by 4 (shifted to the left by two bits) and concatenated with the fetched pointer-level descriptor’s upper 25 bits to produce the physical address of the 8-Kbyte page ...
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Memory Management Unit 'INVALID' 'INVALID' 'INVALID' OTHERWISE EXIT TABLE SEARCH ABBREVIATIONS: PFA - PAGE FRAME ADDRESS DF DESCRIPTOR FIELD WP - ACCUMULATED WRITE- PROTECTION STATUS ASSIGNMENT OPERATOR Figure 4-8. Detailed Flowchart of Table Search Operation 4-10 ENTRY SELECT ...
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TYPE = 'PAGE' OR 'POINTER' FETCH DESCRIPTOR (INDEX*4) (INDEX = RI, PI, OR PGI) IF SCHEDULED, EXECUTE WRITE ACCESS (U PREVIOUS DESCRIPTOR (SEE NOTE) OTHERWISE EXIT TABLE SEARCH 'INVALID' 'RESIDENT' RETURN ...
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Memory Management Unit have an encoding of U-bit = 0, M-bit = 1, and PDT field = 01 or 11. This encoding indicates that the page descriptor is resident, not used, and modified. The processor’s table search algorithm never leaves ...
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DESCRIPTOR FIELD DEFINITIONS. The field definitions for the table- and page- level descriptors are listed in alphabetical order: CM—Cache Mode This field selects the cache mode and accesses serialization as follows Cachable, Writethrough 01 = Cachable, Copyback ...
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Memory Management Unit Physical Address— This 20-bit field contains the physical base address of a page in memory. The logical address supplies the low-order bits of the address required to index into the page. When the page size is 8-Kbyte, ...
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X—Motorola Reserved These bit fields are reserved for future use by Motorola. 4.2.3 Translation Table Example Figure 4-12 illustrates an access example to the logical address $76543210 while in the supervisor mode with an 8-Kbyte memory page size. The RI ...
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Memory Management Unit 4.2.4 Variations in Translation Table Structure Several aspects of the MMU translation table structure are software configurable, allowing the system designer flexibility to optimize the performance of the MMUs for a particular sys- tem. The following paragraphs ...
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When the MC68060 has completed a normal table search, it examines the PDT field of the last entry fetched from the page tables. If the PDT field contains an indirect ($2) encoding, it indicates that the address contained in the ...
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Memory Management Unit ROOT INDEX $76543210 = $3B ...
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ROOT INDEX $76543210 = $3B TABLE ENTRY # ...
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Memory Management Unit updated before the MC68060 allows a page to be accessed. Table 4-1 lists the page descriptor update operations for each combination of U-bit, M-bit, write-protected, and read or write access type. Table 4-1. Updating U-Bit and M-Bit ...
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Page descriptors also contain a supervisor-only (S) bit that can limit access to programs operating at the supervisor privilege level. The protection mechanisms can be used individually or in any combination to protect: • Supervisor address ...
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Memory Management Unit 4.2.6.2 SUPERVISOR ONLY. A second mechanism protects supervisor programs and data without requiring segmenting of the logical address space into supervisor and user address spaces. Page descriptors contain S-bits to protect areas of memory from access by ...
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PRIVILEGE SRP MODE URP URP & SRP POINT TO SAME A LEVEL TABLE NOTE DON'T CARE Figure 4-18. Translation Table Using S-Bit and W-Bit To Set Protection MOTOROLA ...
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Memory Management Unit 4.3 ADDRESS TRANSLATION CACHES The ATCs in the MMUs are four-way set-associative caches that each store 64 logical-to- physical address translations and associated page information similar in form to the corre- sponding page descriptors in memory. The ...
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U1 U0 ENTRY V G FC2 TAG *FOR 4-KBYTE PAGE SIZES, THIS FIELD USES ADDRESS BITS 31–12; FOR 8-KBYTE PAGE SIZES, BITS 31–13. Figure 4-20. ATC Entry and Tag Fields CM—Cache Mode This field selects the cache mode and accesses ...
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Memory Management Unit U0, U1—User Page Attributes These user-defined bits are not interpreted by the MC68060. U0 and U1 are echoed to the UPA0 and UPA1 signals, respectively external bus transfer results from the access. V—Valid When set, ...
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The MMU replaces an invalid entry when the ATC stores a new address translation. When all entries in an ATC set are valid, the ATC selects a valid entry to be replaced, using a pseudo round robin replacement algorithm. A ...
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Memory Management Unit If the paged MMU is disabled (the E-bit in the TCR register is clear) and the TTRs are dis- abled or do not match, then the status and protection attributes are defined by the default translation bits ...
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ATC MISS [( AND (WRITE OR LOCKED RMW CYCLE) ABORT CYCLE TAKE ACCESS ERROR EXCEPTION ( AND (WRITE OR LOCKED RMW CYCLE) ABORT CYCLE TABLE SEARCH OPERATION * Refers to either instruction or data transparent translation ...
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Memory Management Unit 4.6.2 Effect of MDIS on Address Translation The assertion of MDIS prevents the MMUs from performing ATC searches and the execu- tion unit from performing table searches. With address translation disabled, logical addresses are used as physical ...
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SECTION 5 CACHES The MC68060 contains two independent 8-Kbyte, on-chip caches which can be accessed simultaneously for instruction and operand data. The caches improve system performance by providing low latency data to the MC68060 instruction and data pipes. This decouples ...
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Caches EXECUTION UNIT INSTRUCTION FETCH UNIT BRANCH CACHE INSTRUCTION BUFFER pOEP DS DECODE FLOATING- POINT AG EA UNIT CALCULATE FETCH FETCH INT EXECUTE EXECUTE INTEGER UNIT DATA AVAILABLE WRITE-BACK Figure 5-1. MC68060 Instruction ...
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V-bit and D-bit set, indicating that the line has valid entries that have not been writ- ten to memory. A cache line changes states from valid or dirty to invalid if the execution of the CINV or CPUSH ...
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Caches field. The four tags from the selected cache set are compared with the tag reference. If any one of the four tags matches the tag reference and the tag status is either valid or dirty, then a cache hit ...
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Operands of locked instructions (CAS and TAS) and operand references while the lock bit in the bus control register is set which miss in the data cache do not allocate for reads or writes regardless of the caching mode, and ...
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Caches Bits 26–24—Reserved. EBC—Enable Branch Cache 0 = The branch cache is disabled and branch cache information is not used in the branch prediction strategy The on-chip branch cache is enabled. Branches are cached. A predicted branch executes ...
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Internal accesses always bypass the instruction and data caches while CDIS is recognized, and the contents of the caches are unchanged. Disabling the caches with CDIS does not affect ...
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Caches 5.4.1.1 WRITETHROUGH MODE. Accesses to pages specified as writethrough are always written to the external address, although the cycle can be buffered (depending on the state of the ESB bit in the CACR). Writes in writethrough mode are handled ...
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These guarantees apply only when the CM field indicates the precise mode and the accesses are aligned. Regardless of the ...
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Caches 5.5.3 Read Hit On a read hit, the appropriate cache provides the data to the requesting pipe unit. In most cases no bus transaction is performed, and the state of the cache line does not change. However, when a ...
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Invalidating instruction cache lines before writing to the corresponding memory lines can prevent this coherency problem, but only if the data cache line is in writethrough or cache-inhibited mode. A cache ...
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Caches four cycles. The bursting mechanism requires addresses to wrap around so that the entire four long words in the cache line are filled in a single operation. When a cache line read is initiated, the first cycle attempts to ...
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In the case of an instruction cache line fill, the unneeded data from the aborted cycle is completely ignored. The MC68060 supports native retry functionality using the TRA signal, as well as MC68040- compatible retry functionality using TA and ...
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Caches 5.9 STORE BUFFER The MC68060 processor provides a four-entry store buffer (16 bytes maximum). This store buffer is a FIFO buffer that can be used for deferring pending writes to imprecise pages to maximize performance. For operand writes destined ...
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The branch cache implementation is made five-state prediction model based on past execution ...
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Caches of the four cache lines replacing the tag and data contents of the line with the new line infor- mation. Figure 5-6 illustrates the instruction-cache line state transitions resulting from pro- cessor and snoop controller accesses. Transitions are labeled ...
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Table 5-2. Instruction Cache Line State Transitions Cache Operation I1 Read line from memory; supply data to IPU Read Miss IPU and update cache valid state. V1 IPU Read Hit I2 Not Possible. Cache Invalidate or Push I3 ...
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Caches Read misses and write misses to copyback pages cause the cache controller to read a new cache line from memory into the cache. If available, an invalid line in the selected set is updated with the tag and data ...
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Caches Table 5-3. Data Cache Line State Transitions Cache Operation Invalid Cases Read line from memory OPU Read and update cache; Sup- (C,W)I1 Miss ply data to OPU valid state. OPU Read (C,W)I2 Not possible. Hit OPU Write ...
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SECTION 6 FLOATING-POINT UNIT This section does not apply to the MC68LC060 or MC68EC060. Refer to Appendix A MC68LC060 and Appendix B MC68EC060 for details. Floating-point math refers to numeric calculations with a variable decimal point location distinguished ...
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Floating-Point Unit EXECUTION UNIT INSTRUCTION FETCH UNIT BRANCH CACHE INSTRUCTION BUFFER pOEP DS DECODE FLOATING- POINT AG EA UNIT CALCULATE FETCH FETCH INT EXECUTE EXECUTE INTEGER UNIT DATA AVAILABLE WRITE-BACK Figure 6-1. Floating-Point ...
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CONDITION CODE 31 Figure 6-2. Floating-Point User Programming Model 6.1.1 Floating-Point Data Registers (FP7–FP0) The floating-point data registers are analogous to the integer data registers of the M68000 family. The floating-point data registers always contain ...
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Floating-Point Unit EXCEPTION ENABLE BSUN SNAN OPERR OVFL UNFL Figure 6-3. Floating-Point Control Register Format The processor supports four rounding modes specified by the IEEE 754 standard. These modes are round to nearest (RN), round ...
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FLOATING-POINT CONDITION CODE BYTE. The FPCC byte (see Figure 6-4) contains four condition code bits that are set at the end of all arithmetic instructions involving the floating-point data registers. These bits are sign of mantissa (N), zero (Z), ...
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Floating-Point Unit 15 BSUN BRANCH/SET ON UNORDERED SIGNALING NOT-A-NUMBER OPERAND ERROR OVERFLOW Figure 6-6. Floating-Point Exception Status Byte (FPSR) 6.1.3.4 ACCRUED EXCEPTION BYTE. The AEXC byte contains five exception bits (see Figure 6-7) that the IEEE 754 standard requires for ...
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New AEXC Bit IOP OVFL UNFL DZ INEX 6.1.4 Floating-Point Instruction Address Register (FPIAR) For the subset of the floating-point instructions that generate exception traps, the FPU loads the 32-bit FPIAR with the logical address of the instruction before executing ...
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Floating-Point Unit Table 6-4. Single-Precision Real Format Summary Sign (s) Biased Exponent (e) Fraction (f) Total Positive Fraction Negative Fraction Bias of Biased Exponent Range of Biased Exponent Range of Fraction Fraction Relation to Representation of Real Numbers Biased Exponent ...
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Table 6-5. Double-Precision Real Format Summary Sign (s) Biased Exponent (e) Fraction (f) Total Positive Fraction Negative Fraction Bias of Biased Exponent Range of Biased Exponent Range of Fraction Fraction Relation to Representation of Real Numbers Biased Exponent Format Minimum ...
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Floating-Point Unit Table 6-6. Extended-Precision Real Format Summary Sign (s) Biased Exponent (e) Zero, Reserved (u) Explicit Integer Bit (j) Mantissa (f) Total Input Output Positive Mantissa Negative Mantissa Bias of Biased Exponent Range of Biased Exponent ...
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Table 6-6. Extended-Precision Real Format Summary (Continued) Maximum Positive Normalized Minimum Positive Normalized Minimum Positive Denormalized Table 6-7. Packed Decimal Real Format Summary EXP2 63 FRAC15 FRAC14 31 FRAC7 FRAC6 Data Type SM SE 0/1 ...
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Floating-Point Unit The FPU performs all floating-point internal operations in extended precision. It supports mixed-mode arithmetic by converting single- and double-precision operands to extended- precision values before performing the specified operation. The FPU converts all memory data formats to extended ...
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Depending on the selected rounding mode or destination data format in effect, the location of the least significant bit of the mantissa and the locations of the guard, round, and sticky bits in the 67-bit intermediate result mantissa varies. The ...
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Floating-Point Unit RN GUARD AND LSB = 1, ROUND AND STICKY = 0 OR GUARD = 1 ROUND OR STICKY = 1 ADD 1 TO LSB SHIFT MANTISSA RIGHT 1 BIT, ADD 1 TO EXPONENT Figure 6-9. Rounding Algorithm Flowchart ...
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Thus, the term one-half unit in the last place correctly identifies the error bound for this operation. This error specification is the relative error present in the result; the absolute exponent error bound is equal to 2 for the ...
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Floating-Point Unit If no underflow occurs, the intermediate result is rounded according to the user-selected rounding precision and rounding mode. After rounding, the INEX2 bit of the FPSR EXC byte is set accordingly. Finally, the magnitude of the result is ...
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BSUN bit in the FPSR status byte if an unordered condition is present when the conditional test is attempted (IEEE nonaware tests), and 16 tests that do not cause the BSUN bit in the FPSR status ...
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Floating-Point Unit Table 6-9. Floating-Point Conditional Tests Mnemonic Definition EQ Equal NE Not Equal GT Greater Than NGT Not Greater Than GE Greater Than or Equal NGE Not Greater Than or Equal LT Less Than NLT Not Less Than LE ...
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FLOATING-POINT EXCEPTIONS There are two classes of floating-point-related exceptions: nonarithmetic floating-point exceptions and arithmetic floating-point exceptions. The latter relates to the handling of arithmetic exceptions caused by floating-point activity, and the former includes unimple- mented floating-point instructions, unsupported data ...
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Floating-Point Unit Table 6-11. Unimplemented Instructions FACOS FASIN FATAN FATANH FCOSH FETOX FETOXM1 FGETEXP FGETMAN FLOG10 FMOD FSCALE FTRAPcc FMOVEM.X (dynamic register list) F<op>.X #immediate,FPn A floating-point unimplemented instruction exception occurs when the processor attempts to execute an instruction word ...
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The M68060SP emulates the unimplemented floating-point instruction in software, main- taining user-object-code compatibility. Refer to Section 8 Exception Processingfor details about exception vectors and format $2 stack frames. The M68060SP uses the FPIAR to determine the instruction needing emulation and ...
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Floating-Point Unit the floating-point state frame is discarded, and normal execution is resumed by using the RTE instruction. The M68060SP not only emulates the instruction, but in addition, it ensures that if any float- ing-point arithmetic exceptional conditions arise from ...
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The following eight user floating-point arithmetic exceptions are listed in order of priority. • Branch/Set on Unordered (BSUN) • Signaling Not-A-Number (SNAN) • Operand Error (OPERR) • Overflow (OVFL) • Underflow (UNFL) • Divide-by-Zero (DZ) • Inexact 2 (INEX2) • ...
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Floating-Point Unit type exception. The M68060SP passes control over to the user-supplied exception handler, if needed. A single instruction execution can generate multiple exceptions. When multiple exceptions occur with exceptions enabled for more than one exception class, the highest priority ...
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The user BSUN exception handler must execute an FSAVE as its first floating-point instruc- tion. FSAVE allows other floating-point instructions to execute without reporting the BSUN exception again, although none of the state frame values are useful in the execution ...
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Floating-Point Unit 6.6.2.2 TRAP ENABLED RESULTS (FPCR SNAN BIT SET). If the destination is not a floating-point data register (FMOVE OUT instruction), the destination (memory or integer data register) is written with the same data as though the trap were ...
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Table 6-12. Possible Operand Errors Exceptions Instruction FADD [(+ ) + (– [(– FDIV (0 FMOVE to B,W,or L Integer overflow, source is nonsignaling NAN or FMUL One operand is 0 and other is ...
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Floating-Point Unit the user OPERR handler post-instruction exception. If desired, the user OPERR han- dler can overwrite the default result. If the destination is a floating-point data register, the register is not modified. Control is passed to the ...
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FPCR exception enable byte is set and the corresponding INEX bit in the FPSR EXC byte is also set). 6.6.4.1 TRAP DISABLED RESULTS (FPCR OVFL BIT CLEARED). The values defined in Table 6-13 are stored in the destination based on ...
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Floating-Point Unit intermediate result format. When such an overflow occurs (called a catastrophic overflow), the exception operand exponent value is set to $0000. This value is easily distinguished from the exception operand exponent values produced by normal overflow processing. If ...
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If the destination is a floating-point data register, the register is not affected, and a pre-instruction exception is reported. If the destination is a memory or integer data register, then an undefined result is stored, and a ...
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Floating-Point Unit The user UNFL handler must execute an FSAVE instruction as the first floating-point instruc- tion to prevent further exceptions from reporting. The address of the instruction that causes the overflow is available to the user UNFL handler in ...
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Table 6-15. Possible Divide-by-Zero Exceptions Instruction FDIV Source operand = 0 and floating-point data register is not a NAN zero FLOG10 Source operand = 0 FLOG2 Source operand = 0 FLOGN Source operand = 0 FTAN Source operand ...
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Floating-Point Unit The INEX2 exception is the condition that exists when any operation, except the input of a packed decimal number, creates a floating-point intermediate result whose infinitely precise mantissa has too many significant bits to be represented exactly in ...
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When the user INEX exception handler has completed, the floating-point frame may be dis- carded. The RTE instruction must be executed to return to normal instruction flow. The IEEE 754 standard specifies that inexactness should be sig- naled on overflow ...
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Floating-Point Unit 15 Frame Format $00—Null Frame $60—Idle Frame $E0—Exception Frame V2–V0—Exception Vector 000—BSUN 001—INEX2 | INEX1 010—DZ 011—UNFL 100—OPERR 101—OVFL 110—SNAN 111—UNSUP Figure 6-11. Status Word Contents FSAVE on the MC68060 only generates one size frame (three long words), ...
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FSAVE instruction to clear the internal exception status bit in the FPU. To return to normal operation, the user exception handler may either clear the most significant bit of the frame format (changing the frame ...
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SECTION 7 BUS OPERATION The MC68060 bus interface supports synchronous data transfers between the processor and other devices in the system. This section provides a functional description of the bus, the signals that control the bus, and the bus cycles ...
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Bus Operation CLK CLKEN OUTPUTS INPUTS NOTES Propagation delay of signal relative to CLK rising edge Output hold time relative to CLK rising edge Required input setup time ...
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CLK CLKEN BCLK BB or TIP THREE-STATING FROM ASSERTED STATE 7.2 FULL-, HALF-, AND QUARTER-SPEED BUS OPERATION AND BCLK To simplify the description of full-, half-, and quarter-speed bus operation, the term “bus clock” or “BCLK” is introduced to describe ...
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Bus Operation of BCLK represent the rising edges of CLK in which CLKEN is asserted. However, there are cases in which the BCLK concept does not apply. The BCLK concept does not apply to the IPLx and RSTI input signals. ...
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LE—Lock End Bit 0 = Negate external LOCKE signal Assert external LOCKE signal. SLE—Shadow Copy, Lock End Bit 0 = LOCKE asserted at time of exception LOCKE negated at time of exception. The external LOCK signal ...
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Bus Operation REGISTER OP0 MULTIPLEXER EXTERNAL D31–D24 DATA BUS ADDRESS BS0 $xxxxxxx0 bidirectionally with 32-, 16-, or 8-bit peripherals and memories. It dynamically recognizes the size of the selected peripheral or memory device and ...
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Table 7-1. Data Bus Requirements for Read and Write Cycles Signal Encoding Transfer Size SIZ1 SIZ0 Byte Word 1 0 Long Word 0 0 Line 1 1 Table 7-1 lists ...
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Bus Operation A0 A1 SIZ0 SIZ1 PAL16L8 U1 MC68060 Byte Data Select Generation SIZ0 SIZ1 GND NC UUD UMD LMD LLD VCC /UUD = /A0 * /A1 + /SIZ1 ...
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Table 7-2. Summary of Access Types vs. Bus Signal Encoding Data Normal Bus Cache Data/ Signal Push Code Access Access Access Access A31–A0 Address Address MMU UPA1, $0 Source 1 UPA0 SIZ1, L/Line B/W/L/Line Long Word SIZ0 TT1, TT0 $0 ...
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Bus Operation Figure 7-9 illustrates the transfer of a long-word operand from an odd address requiring more than one bus cycle. For the first transfer or bus cycle, the SIZx signals specify a byte transfer, and the byte offset is ...
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C1 BCLK A31–A2 MISCELLANEOUS ATTRIBUTES TS TIP R/W A1–A0 SIZ1–SIZ0 TA BS0 BS1 BS2 BS3 D31–D24 D23–D16 D15–D8 D7–D0 Figure 7-11. Misaligned Long-Word Read Bus Cycle Timing The combination of operand size and alignment determines the number of bus cycles ...
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Bus Operation bus cycle. The MC68060 system designer and programmer should account for these effects, particularly in time-critical applications. Table 7-3. Memory Alignment Influence on Noncachable and Writethrough Bus Cycles Transfer Size Instruction Byte Operand Word Operand Long-Word Operand *Where ...
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Accesses that do not allocate in the data cache on a read miss (exception vector fetch- es, and exception stack deallocation for an RTE instruction) • The first transfer of a line read is terminated with transfer burst inhibit ...
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Bus Operation C1 BCLK ADDRESS AND ATTRIBUTES R/W A1–A0 SIZ1–SIZ0 TS TIP TA SAS BS0 BS1 BS2 BS3 D31–D24 D23–D16 D15–D8 D7–D0 BYTE READ NOTE assumed that the acknowledge termination ignore state capability is disabled. Figure 7-13. Byte, ...
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Clock 2 (C2) During C2, the processor negates TS. The selected peripheral device uses R/W, SIZ1, SIZ0, A1, and A0 or BSx to place its information on the data bus. With the exception of the R/W signal, these signals also ...
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Bus Operation cycles, the bus controller still treats the four transfers as a single line bus cycle and does not allow other unrelated processor accesses or bus arbitration to intervene between the trans- fers. TBI is ignored after the first ...
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PROCESSOR 1) SET R/W TO READ 2) DRIVE ADDRESS ON A31–A0 3) DRIVE UP A1–UPA0, TT1–TT0, TM2–TM0, CIOUT, TLN1–TLN0, LOCK, LOCKE, BS3–BS0 4) DRIVE SIZ1–SIZ0 TO LINE 5) ASSERT TS FOR ONE BCLK 6) ASSERT TIP 7) ASSERT SAS IMMEDIATELY ...
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Bus Operation BCLK A31–A4 A1–A0 MISCELLANEOUS ATTRIBUTES R/W SIZ1–SIZ0 BS3–BS0 CIOUT CLA A3–A2 TS TIP SAS TA TBI D31–D0 NOTE assumed that the acknowledge termination ignore state capability is disabled. Figure 7-15. Line Read Transfer Timing abled, SAS ...
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The registered data and the value of TCI are then passed to the appropriate memory unit. If TBI was negated with the assertion of TA, the processor continues the cycle with C3. Otherwise, if TBI was asserted, the line ...
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Bus Operation PROCESSOR 1) INCREMENT A3–A2 2) DRIVE SIZ1–SIZ0 TO LONG 3) ASSERT TS FOR ONE BCLK 4) ASSERT SAS IMMEDIATELY IF ACKNOWLEDGE TERMINATION IGNORE STATE CAPABILITY DISABLED. ELSE, ASSERT SAS AFTER READ PRIMARY IGNORE STATE COUNTER HAS EXPIRED 1) ...
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C1 BCLK A31–A4 A1–A0 MISCELLANEOUS ATTRIBUTES R/W SIZ1–SIZ0 LINE BS3–BS0 CIOUT CLA A3– TIP SAS TA TBI D31–D0 INHIBITED LINE READ NOTE assumed that the acknowledge termination ignore state capability is disabled. Figure 7-17. Burst-Inhibited Line ...
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Bus Operation PROCESSOR 1) SET R/W TO WRITE 2) DRIVE ADDRESS ON A31–A0 3) DRIVE UPA1–UPA0, TT1–TT0, TM2–TM0, CIOUT, TLN1–TLN0, LOCK, LOCKE, BS3–BS0 4) DRIVE SIZ1–SIZ0 TO BYTE, WORD, OR LONG 5) ASSERT TS FOR ONE BCLK 6) ASSERT TIP ...
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C1 BCLK MISCELLANEOUS ATTRIBUTES R/W A1–A0 SIZ1–SIZ0 TS TIP TA SAS BS0 BS1 BS2 BS3 PRE D31–D0 DRIVE BYTE WRITE NOTE assumed that the acknowledge termination ignore state capability is disabled. Figure 7-19. Long-Word Write Bus Cycle Timing ...
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Bus Operation Clock 1 (C1) The write cycle starts in C1. During C1, the processor places valid values on the address bus and transfer attributes. The processor asserts TS during C1 to indicate the beginning of a bus cycle. If ...
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TIP during the next clock. The processor also three-states the data bus during the next clock following termination of the write transfer. 7.7.4 Line Write Cycles The processor uses line write bus cycles to access a 16-byte operand ...
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Bus Operation PROCESSOR 1) SET R/W TO WRITE 2) DRIVE ADDRESS ON A31–A0 3) DRIVE UPA1–UPA0, TT1–TT0, TM2–TM0, CIOUT, TLN1–TLN0, LOCK, LOCKE, BS3–BS0 4) DRIVE SIZ1–SIZ0 TO LINE 5) ASSERT TS FOR ONE BCLK 6) ASSERT TIP 7) ASSERT SAS ...
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PROCESSOR 1) INCREMENT A3–A2 2) DRIVE SIZ1–SIZ0 TO LONG 3) ASSERT TS FOR ONE BCLK 4) ASSERT SAS IMMEDIATELY IF ACKNOWLEDGE TERMINATION IGNORE STATE CAPABILITY DISABLED. ELSE, ASSERT SAS AFTER WRITE PRIMARY IGNORE STATE COUNTER HAS EXPIRED 5) PLACE DATA ...
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Bus Operation BCLK A31–A4 A1–A0 MISCELLANEOUS ATTRIBUTES R/W SIZ1–SIZ0 BS3–BS0 CIOUT CLA A3–A2 TS TIP SAS TA TBI D31–D0 NOTE assumed that the acknowledge termination ignore state capability is disabled. Figure 7-22. Line Write Bus Cycle Timing sertion ...
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MC68060 asserts the LOCK signal to indicate that an indi- visible operation is occurring and asserts the LOCKE signal for the last write bus cycle to indicate completion of the locked sequence. In addition to LOCK and ...
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Bus Operation C1 BCLK A31–A2 A1–A0 MISCELLANEOUS ATTRIBUTES R/W SIZ1–SIZ0 BS3–BS0 CIOUT LOCK LOCKE TS TIP SAS TA D31–D0 NOTE assumed that the acknowledge termination ignore state capability is disabled. Figure 7-23. Locked Bus Cycle for TAS Instruction ...
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When the processor recognizes TA at the end of the last read transfer for the locked bus cycle, it negates TIP during the first half of the next clock. Clock Idle (CI) The processor does not assert any new control ...
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Bus Operation BUSCR is used to control the LOCK and LOCKE outputs. Refer to 7.4 Bus Control Regis- ter for the format of the BUSCR. Emulation of these instructions is done as part of the MC68060 software package (M68060SP). Refer ...
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CLK TS TA CLA A3–A2 DATA (WRITE CYCLE) DATA (READ CYCLE) RAS CAS DRAM ADDRESS ROW Figure 7-24. Using CLA in a High-Speed DRAM Design and debounce these signals. An interrupt request that is held constant for two consecutive CLK ...
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Bus Operation instruction boundary (following any higher priority exception). The IPEND signal negates after the interrupt acknowledge bus cycle. CLK IPL2–IPL0 IPEND IPLx RECOGNIZED IPLx SYNCHRONIZED COMPARE REQUEST WITH MASK IN SR IPEND is intended to provide status information, and ...
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INTERRUPT ACKNOWLEDGE CYCLE (TERMINATED NORMALLY). When the MC68060 processes an interrupt exception, it performs an interrupt acknowledge bus cycle to obtain the vector number that contains the starting location of the interrupt exception han- dler. Some interrupting devices have ...
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Bus Operation 1) IPEND RECOGNIZED. WAIT FOR INSTRUC- TION BOUNDARY OR LOCK NEGATED 2) SET R/W TO READ 3) DRIVE ADDRESS ON A31–A0 TO $FFFFFFFF 4) DRIVE UPA1–UPA0 = 0 5) DRIVE TT1–TT0 = 3 6) DRIVE TM2–TM0 = INTERRUPT ...
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BCLK A31–A0 MISCELLANEOUS ATTRIBUTES TT1–TT0 UPA1–UPA0 SIZ1–SIZ0 R/W TM2–TM0 BS2–BS0 BS3 CIOUT TS TIP SAS TA AVEC D31–D8 D7–D0 Figure 7-28. Interrupt Acknowledge Bus Cycle Timing Note that the acknowledge termination ignore state capability is applicable to the breakpoint acknowledge ...
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Bus Operation BCLK A31–A0 MISCELLANEOUS ATTRIBUTES TT1–TT0 UPA1–UPA0 SIZ1–SIZ0 R/W TM2–TM0 BS2–BS0 BS3 CIOUT TS TIP SAS TA AVEC D31–D0 Figure 7-29. Autovector Interrupt Acknowledge Bus Cycle Timing 7.8.2.1 LPSTOP BROADCAST CYCLE. The execution of an LPSTOP instruction gener- ates ...
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PROCESSOR 1) SET R/W TO READ 3) DRIVE ADDRESS ON A31–A0 TO $00000000 4) DRIVE UPA1–UPA0 = 0 5) DRIVE TT1–TT0 = 3 6) DRIVE TM2–TM0 = 0 7) DRIVE TLN1–TLN0 = 0 8) ASSERT BS0 9) NEGATIVE CIOUT, LOCK, ...
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Bus Operation BCLK A31–A0 MISCELLANEOUS ATTRIBUTES TT1–TT0 UPA1–UPA0 SIZ1–SIZ0 R/W TM2–TM0 BS3–BS1 BS0 CIOUT TS TIP SAS TA D31–D0 Figure 7-31. Breakpoint Interrupt Acknowledge Bus Cycle Timing To exit the LPSTOP mode, the processor CLK must be restarted for at ...
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PROCESSOR 1) SET R/W TO WRITE 2) DRIVE ADDRESS ON A31–A0 TO $FFFFFFFF 3) DRIVE UPA1–UPA0 = 0 4) DRIVE TT1–TT0 = 3 5) DRIVE TM2–TM0 = 0 6) DRIVE TLN1–TLN0 = 0 7) ASSERT BS3–BS2 8) NEGATE CIOUT, LOCK, ...
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Bus Operation C1 BCLK A31–A0 MISCELLANEOUS ATTRIBUTES TT1–TT0 SIZ1–SIZ0 R/W TM2–TM0 BS1–BS0 BS3–BS2 CIOUT TS TIP SAS TA D15– BTT PST4–PST0 BROADCAST Figure 7-33. LPSTOP Broadcast Bus Cycle Timing, BG Negated 7-42 C2 $FFFFFFFE WORD PRE DRIVE ...
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C1 BCLK A31–A0 MISCELLANEOUS ATTRIBUTES TT1–TT0 SIZ1–SIZ0 R/W TM2–TM0 BS1–BS0 BS3–BS2 CIOUT TS TIP SAS TA D15–D0 DRIVE BTT PST4–PST0 LPSTOP BROADCAST Figure 7-34. LPSTOP Broadcast Bus Cycle Timing, BG Asserted MOTOROLA C2 $FFFFFFFE WORD PRE NO ...
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Bus Operation Figure 7-35 illustrates a flowchart for exiting the LPSTOP mode, and Figure 7-36 illustrates the bus activity when exiting the LPSTOP mode, assuming that an interrupt is used to awaken the processor and that the bus is initially ...
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BCLK A31–A0 MISCELLANEOUS ATTRIBUTES TS TIP SAS TA, TEA, TRA, TCI, TBI, AVEC SNOOP, BGR, MDIS, CDIS, CLA D31– BTT PST4–PST0 IPL2–IPL0 CLK READY FOR MORE THAN 8 CLKS AND 2 BCLKS Figure 7-36. Exiting LPSTOP Mode ...