MC68LC060RC66 Freescale Semiconductor, MC68LC060RC66 Datasheet - Page 265

• Manufacturer Part Number: MC68LC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes
*LPSAMPLE is not supported on version 0000. See Figure 9-2 in 9.1.3.1 Idcode Register .
The EXTEST, SAMPLE/PRELOAD, and BYPASS instructions are required by IEEE 1149.1.
IDCODE is an optional public instruction supported by the MC68060. CLAMP and HIGHZ
are optional public instructions that are supported by the MC68060 and are described the
1149.1-1993 standard. LPSAMPLE is a Motorola-defined public instruction.
All encodings other than these are private instructions for Motorola internal use only.
Improper or unauthorized use of these instructions could result in potential internal damage
to the device and can cause external signal contention since these tests operate internal
registers, data path, and memory array logic and can drive random signal values on both
the input and output pins.
9.1.2.1 EXTEST. The external test instruction (EXTEST) selects the 214-bit boundary scan
register. The EXTEST instruction forces all output pins and bidirectional pins configured as
outputs to the fixed values that are preloaded (with the PRELOAD instruction) and held in
the boundary scan update registers. The EXTEST instruction can also be used to configure
the direction of bidirectional pins and establish high-impedance states on some pins. The
EXTEST instruction becomes active on the falling edge of TCK in the update-IR state when
the data held in the instruction shift register is equivalent to $0.
It is recommended that the boundary scan register bit equivalent to the RSTI pin be pre-
loaded with the assert value for system reset prior to application of the EXTEST instruction.
This will ensure that EXTEST asserts the internal reset for the MC68060 system logic to
force a predictable benign internal state while forcing all system output pins to fixed values.
However, if it is desired to hold the processor in the LPSTOP state when applying the
EXTEST instruction, do not preload the boundary scan register bit equivalent to the RSTI
pin with an assert value because this action forces the processor out of the LPSTOP state.
9-4
MFG-TEST9
MFG-TEST1
MFG-TEST2
MFG-TEST3
MFG-TEST4
MFG-TEST5
MFG-TEST6
MFG-TEST7
MFG-TEST8
LPSAMPLE
Instruction
SAMPLE
BYPASS
EXTEST
IDCODE
CLAMP
HIGHZ
Acro
CMP
SMP
BYP
EXT
LPS
IDC
HIZ
—
—
—
—
—
—
—
—
—
Required
Required
Required
Optional
Optional
Optional
Private
Private
Private
Private
Private
Private
Private
Private
Private
Public
Class
Table 9-2. JTAG Instructions
M68060 USER’S MANUAL
IR3–IR0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Selects the boundary scan register for data operations while
input pins are isolated *
Select boundary scan register to apply fixed values to outputs
For Motorola Internal Manufacturing Test use only
For Motorola Internal Manufacturing Test use only
Selects boundary scan register for shift, sample and preload
Defaults to select the ID code register
Selects bypass while fixing output values
Selects bypass while three-stating all chip outputs
For Motorola Internal Manufacturing Test use only
For Motorola Internal Manufacturing Test use only
For Motorola Internal Manufacturing Test use only
For Motorola Internal Manufacturing Test use only
For Motorola Internal Manufacturing Test use only
For Motorola Internal Manufacturing Test use only
For Motorola Internal Manufacturing Test use only
Selects the bypass register for data operations
Instruction Summary
MOTOROLA