MC68LC060RC66 Freescale Semiconductor, MC68LC060RC66 Datasheet - Page 168

• Manufacturer Part Number: MC68LC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Figure 7-12 is a flowchart for byte, word, and long-word read transfers. Bus operations are
similar for each case and vary only with the size indicated and the portion of the data bus
used for the transfer. Figure 7-13 is a functional timing diagram for byte, word, and long-
word read transfers.
Clock 1 (C1)
MOTOROLA
• Accesses that do not allocate in the data cache on a read miss (exception vector fetch-
• The first transfer of a line read is terminated with transfer burst inhibit (TBI), forcing com-
The read cycle starts in C1. During C1, the processor places valid values on the address
bus and transfer attributes. For user and supervisor mode accesses, which the corre-
sponding memory unit translates, the user-programmable attribute signals (UPAx) are
driven with the values from the matching user bits (U1 and U0). The transfer type (TTx)
and transfer modifier (TMx) signals identify the specific access type. The read/write (R/W)
signal is driven high for a read cycle. Cache inhibit out (CIOUT) is asserted since the ac-
cess is identified as noncachable. Refer to Section 4 Memory Management Unit for in-
formation on the MC68060 and MC68LC060 memory units and Appendix B MC68EC060
for information on the MC68EC060 memory unit.
es, and exception stack deallocation for an RTE instruction)
pletion of the line access using three additional long-word read transfers
1) SET R/W TO READ
2) DRIVE ADDRESS ON A31–A0
3) DRIVE UPA1–UPA0, TM2–TM0, CIOUT,
4) DRIVE SIZ1–SIZ0 TO BYTE, WORD, OR LONG
5) ASSERT TS FOR ONE BCLK
6) ASSERT TIP
7) ASSERT SAS IMMEDIATELY IF
Figure 7-12. Byte, Word, and Long-Word Read Cycle Flowchart
1) REGISTER DATA
2) NEGATE LOCK, LOCKE IF NECESSARY
TLN1–TLN0, LOCK, LOCKE, BS3–BS0
ACKNOWLEDGE TERMINATION IGNORE
STATE CAPABILITY DISABLED. ELSE,
ASSERT SAS AFTER READ PRIMARY
IGNORE STATE COUNTER HAS EXPIRED
1) NEGATE TIP OR START NEXT CYCLE
PROCESSOR
M68060 USER’S MANUAL
1) DECODE ADDRESS
2) PLACE DATA ON APPROPRIATE BYTE
3) ASSERT TA AROUND RISING EDGE OF
1) THREE-STATE D31–D0
LANES BASED ON SIZ1–SIZ0, A1–A0, OR
BS3–BS0
BCLK.
SYSTEM
Bus Operation
7-13