MC68LC060RC66 Freescale Semiconductor, MC68LC060RC66 Datasheet - Page 307

• Manufacturer Part Number: MC68LC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

MOTOROLA
4. The OEP is able to complete all memory accesses without any stall conditions due to
5. All data accesses are assumed to be aligned on the same byte boundary as the oper-
6. Certain instructions perform a pipeline synchronization prior to their actual execution.
The occurrence of any cache miss will add a specific number of cycles to the base exe-
For instructions which generate external bus cycles as part of their execution (e.g.,
If the operand alignment fails these suggested guidelines, the reference is termed a
Once all these conditions are satisfied, the instruction begins its actual execution.
For the instruction timings listed in the timing data, the following assumptions are made
ATC or cache misses and/or operand data cache bank busy. This means all operand
data memory references produce address translation cache hits, are mapped to cach-
able pages, and produce hits in the operand data cache. Additionally, branch instruc-
tions are assumed to produce an instruction cache hit for the target address instruction
fetch.
cution time of an instruction (see 10.3 Cache and atc Performance Degradation
Times and 10.4 Effective Address Calculation Times ).
MOVE16, CPUSH), a 2-1-1-1 memory system is assumed.
and size:
misaligned access. The processor is required to make multiple accesses to obtain any
misaligned operand. For copyback or writethrough pages, one processor clock cycle
must be added to the instruction execution time for a misaligned read reference. Two
clock cycles must be added for a misaligned write or read-modify-write.
For these opcodes, the instruction enters the pOEP and then waits until the following
conditions are met:
for these pipeline synchronization instructions:
mov.l<mem>,An
<op> <ea using An>
•16-bit operands aligned on 0-modulo-2 addresses
•32-bit operands aligned on 0-modulo-4 addresses
•64-bit operands aligned on 0-modulo-8 addresses
•96-bit operands aligned on 0-modulo-4 addresses
•The instruction cache is in a quiescent state with all outstanding cache misses
•The data cache is in a quiescent state with all outstanding cache misses com-
•The push and write buffers are empty.
•The execution of all previous instructions has completed.
•The instruction cache is not processing any cache misses.
•The data cache is not processing any cache misses.
•The push and write buffers are empty.
•The OEP has dispatched an instruction or instruction-pair on the previous cycle.
completed.
pleted.
M68060 USER’S MANUAL
Instruction Execution Timing
10-11