MC68LC060RC66 Freescale Semiconductor, MC68LC060RC66 Datasheet - Page 380

• Manufacturer Part Number: MC68LC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

bit is clear in the FPCR. Therefore, no software assistance is required in this case to main-
tain MC68881/882 compatibility. An M68060FPSP handler, _fpsp_inex, is provided for en-
abled inexact exceptions for the following reasons:
C.3.2.3.4 Divide-by-Zero Exception. Only opclass zero and two instructions can take the
divide-by-zero floating-point (DZ) exception. The processor takes exception vector number
fifty with a type zero stack frame for this case. The FSAVE frame for the DZ exception is
valid and contains the source operand converted to extended precision.
The divide-by-zero exception is a maskable exception on the MC68060 for the trap disabled
case. The FPU produces the correct result when the DZ bit in the FPCR is clear. No
M68060FPSP assistance is required to maintain MC68881/882 compatibility for DZ dis-
abled. A handler, _fpsp_dz, is provided for enabled DZ exceptions. This M68060FPSP han-
dler converts the FSAVE source operand to extended precision if the source operand is a
zero in single or double format. The handler then passes control to the user enabled divide-
by-zero exception handler (_real_dz). No parameters are passed to the user DZ exception
handler from the M68060FPSP package since the package provides the illusion that it never
existed.
C.3.2.3.5 Branch/Set on Unordered Exception. The MC68060 processor provides the
correct results and actions for both the branch/set on unordered (BSUN) exception enabled
and disabled cases. Therefore, no M68060FPSP assistance is required for MC68881/882
compatibility.
MOTOROLA
• For opclass two pre-instruction exceptions, the processor does not store the default re-
• In addition, for opclass two pre-instruction exceptions using a single or double source
• For opclass three post-instruction exceptions, the processor does not store the default
sult to the destination floating-point register before taking the enabled inexact excep-
tion. The MC68881/882 stored the default result in this scenario. Therefore, to maintain
compatibility, the M68060FPSP inexact exception handler calculates and stores the de-
fault result before passing control to the user enabled inexact exception handler
(_real_inex). No parameters are passed to the user enabled inexact exception handler
since the M68060FPSP handler provides the illusion that it never existed.
format with an infinity, denorm, or zero source operand, the processor does not create
the correct extended-precision value for the FSAVE frame. The correct extended-pre-
cision value is also not created when the source format is a longword integer. The
M68060FPSP inexact handler converts the value in the FSAVE frame to extended-pre-
cision format for these cases before passing control to the user enabled inexact excep-
tion handler (_real_inex).
result to the destination memory or integer data register before taking the enabled in-
exact exception. The MC68881/882 stored the default result in this scenario. Therefore,
to maintain compatibility, the M68060FPSP inexact exception handler calculates and
stores the default result before passing control to the user enabled inexact exception
handler (_real_inex). No parameters are passed to the user enabled inexact exception
handler since the M68060FPSP handler provides the illusion that it never existed.
M68060 USER’S MANUAL
MC68060 Software Package
C-19