MC68LC060RC66 Freescale Semiconductor, MC68LC060RC66 Datasheet - Page 291

• Manufacturer Part Number: MC68LC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes
There are two ways to halt the processor. The first method uses the debug pipe control
mode command “halt the processor”. This command causes the processor to gracefully halt
instruction execution. When this command is received, the processor posts a pending halt
condition an then waits for an interruptible point to be reached. Once the interruptible point
is encountered, the processor halts instruction execution and signals the status with the
PSTx signals.
The second method uses the HALT instruction. The HALT instruction is a 16-bit privileged
instruction ($4AC8 encoding) and is new with the MC68060 instruction set. When the pro-
cessor executes this instruction, the pipeline is synchronized and then the processor enters
the halted state. Once halted, the processor drives a unique PSTx output encoding.
The halt state is different than the stopped state since no interrupts are processed while in
this mode. To enable the processor to exit the halted state and resume normal instruction
execution, the “restart the processor” command is issued through the debug pipe control
mode. When this command is received, the processor continues normal instruction execu-
tion by forcing an instruction fetch to the next sequential instruction address contained in the
program counter (PC). Using this approach, any commands that may have been executed
while halted (like patching memory and clearing the instruction cache) will be correctly han-
dled by the processor when restarting. For instance, if the HALT instruction was used to
place the processor into the halted state, instruction execution resumes at the instruction fol-
lowing the HALT instruction.
The commands $06 and $07 can be used to force nonpipelined operation. When operating
in nonpipelined execution mode, the processor’s OEP performs a single dispatch (of an
instruction or instruction pair) and immediately enters a pipeline hold state that prevents sub-
sequent dispatches. After the instruction/instruction pair has completed execution of all OEP
pipeline stages, the hold state is reset to release another single dispatch. To allow toggling
between normal operation and the nonpipelined, single-pipe operation, a new MC68060
instruction, the PULSE instruction, can be used by issuing command $03.
The PULSE instruction is a 16-bit user mode instruction that uses the $4ACC opcode. The
PULSE instruction has been added to the instruction set primarily to provide a unique encod-
ing of the PSTx outputs for external triggering purposes. Additionally, with command $03, it
is used to allow the capability to toggle in and out of nonpipelined operation mode. When
the PULSE instruction is executed in user mode, the PSTx encoding $04 will exist for one
CLK period. When the PULSE instruction is executed in supervisor mode, the PSTx encod-
ing of $14 will exist for one CLK period.
When using the PULSE instruction to toggle in and out of nonpipelined mode, A NOP
instruction must follow the PULSE instruction to ensure proper operation. All nonpipelined
modes of operation are disabled through the “reset all nonpipelined modes” command $04.
Commands $08 to $0C are used to insert instructions into the primary OEP. These instruc-
tions are executed immediately. Accordingly, any number of commands can be shifted into
the processor while halted. The execution time of the instruction is equal to the normal exe-
cution time of the instruction plus three CLK periods, where the first cycle corresponds to
the cycle when “command valid” is asserted. It is the responsibility of the external logic
9-30
M68060 USER’S MANUAL
MOTOROLA