MC68LC060RC66 Freescale Semiconductor, MC68LC060RC66 Datasheet - Page 196

• Manufacturer Part Number: MC68LC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

In normal applications, the requirement to keep the above-mentioned control signals
negated while exiting the LPSTOP condition should be easy to meet, since most of these
signals should already have pullup resistors and keeping alternate master activity from
occurring would allow the pullup resistors to keep these control signals negated. However,
strict compliance for the BGR and AVEC signals is not necessary because these signals are
significant only during locked sequences (BGR) and interrupt acknowledge cycles (AVEC),
neither of which is pending when exiting the LPSTOP condition.
MOTOROLA
10) ASSERT TS FOR ONE BCLK
11) ASSERT TIP
12) DRIVE D15–D0 TO IMMEDIATE VALUE
13) ASSERT SAS IMMEDIATELY IF
1) IF NORMAL OR BUS ERROR TERMINATION
2) IF RETRY TERMINATION, RETRY LPSTOP
1) SET R/W TO WRITE
2) DRIVE ADDRESS ON A31–A0 TO $FFFFFFFF
3) DRIVE UPA1–UPA0 = 0
4) DRIVE TT1–TT0 = 3
5) DRIVE TM2–TM0 = 0
6) DRIVE TLN1–TLN0 = 0
7) ASSERT BS3–BS2
8) NEGATE CIOUT, LOCK, LOCKE, BS1–BS0
9) DRIVE SIZ1–SIZ0 TO BYTE
1) NEGATE TIP
2) THREE-STATE ENTIRE BUS IF BG NEGATED
1) PERFORM INTERNAL CLEANUP
2) ENTER LPSTOP MODE
3) DRIVE PST4–PST0 = $16
ACKNOWLEDGE TERMINATION IGNORE
STATE CAPABILITY DISABLED; ELSE,
ASSERT SAS AFTER WRITE PRIMARY
IGNORE STATE COUNTER HAS EXPIRED
ENTER LPSTOP MODE AFTER COMPLETION
OF BUS CYCLE
BROADCAST CYCLE
AT BUS CYCLE TERMINATION; ELSE, DRIVE
BUS SIGNALS HIGH
Figure 7-32. LPSTOP Broadcast Cycle Flowchart
PROCESSOR
M68060 USER’S MANUAL
1) DECODE ADDRESS AND ATTRIBUTES
2) ASSERT TA, TEA, OR TRA FOR ONE BCLK
3) DRIVE BG
4) TEMPORARILY CEASE ALL ALTERNATE
1) CONTINUE ALTERNATE MASTER ACTIVITY
2) STOP CLK AT LOW STATE IF NEEDED
3) BUS ARBITRATION MUST RECOGNIZE
MASTER ACTIVITY
AS NECESSARY WHEN PST4–PST0 = $16
THAT PROCESSOR DOES NOT PERFORM
TS-BTT TRACKING WHILE IN LPSTOP MODE
SYSTEM
Bus Operation
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