ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 136

• Manufacturer Part Number: ENC624J600-I/PT
• Description: IC ETHERNET CTRLR W/SPI 64-TQFP
• Manufacturer: Microchip Technology

Specifications of ENC624J600-I/PT

• Package / Case: 64-TFQFP
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC424J600/624J600
To encrypt a block using OFB mode:
1.
2.
3.
4.
5.
6.
7.
8.
To decrypt a block using OFB mode:
1.
2.
3.
4.
5.
FIGURE 15-5:
DS39935C-page 134
Load the encryption key as described in
Section 15.3.1 “Key Support” .
Set AESOP<1:0> (ECON1<10:9>) to ‘ 00 ’.
Copy the Initialization Value (IV) to TEXTA at
7C20h.
Set AESST (ECON1<11>)
encryption.
Copy the plaintext message to TEXTB at
7C30h.
Wait for the hardware to clear AESST.
Read the ciphertext message from XOROUT at
7C40h.
Repeat steps 4 through 7 for subsequent blocks.
The encryption output from the previous block
automatically becomes the IV for the following
block.
Load the encryption key as described in
Section 15.3.1 “Key Support” . Note that this
mode does not make use of a decryption key.
Set AESOP<1:0> to ‘ 00 ’.
Copy the Initialization Value (IV) to TEXTA at
7C20h.
Set AESST to initiate the encryption.
Copy the ciphertext message to TEXTB at
7C30h.
CTR
DATA
Plaintext
ENCRYPTER
0
Ciphertext
0
Key
KEY
ENCRYPTION
0
CTR ENCRYPTION AND DECRYPTION
CTR
DATA
Plaintext
ENCRYPTER
to initiate the
1
Ciphertext
1
Key
KEY
1
6.
7.
8.
The context for OFB mode consists of both the AES
encryption key and the encryption output from the most
recent block. Save the encryption block output from
TEXTA at 7C20h to be used as the IV when resuming
the operation for additional blocks.
15.3.3.5
Counter mode is not directly supported by hardware,
but can be implemented with software assistance. In
CTR mode, a counter is used as the input to the
encryption block. The encrypted output is then XORed
with the plaintext to yield the ciphertext, or vice versa.
The counter does not necessarily need to be a true
counter; any practically non-repeating function will
suffice. When using CTR mode, the application must
load the counter value before each block.
Since each block depends on the counter value, iden-
tical subsequent plaintext blocks will yield different
ciphertext blocks. Whether or not these blocks are
independent will depend on the selected counter
function. Figure 15-5 shows the use of CTR mode for
encryption and decryption.
Wait for the hardware to clear AESST.
Read the plaintext message from XOROUT at
7C40h.
Repeat steps 4 through 7 for subsequent blocks.
CTR
DATA
Ciphertext
ENCRYPTER
0
Plaintext
Counter Mode (CTR)
0
Key
KEY
DECRYPTION
0
 2010 Microchip Technology Inc.
CTR
DATA
Ciphertext
ENCRYPTER
1
Plaintext
1
Key
KEY
1