ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 93
![IC ETHERNET CTRLR W/SPI 64-TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
ENC624J600-I/PT
Manufacturer Part Number
ENC624J600-I/PT
Description
IC ETHERNET CTRLR W/SPI 64-TQFP
Manufacturer
Microchip Technology
Specifications of ENC624J600-I/PT
Package / Case
64-TFQFP
Controller Type
Ethernet Controller
Interface
SPI
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
96mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Input Voltage Range (max)
5.5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3 V to 3.6 V
Supply Current (max)
117 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ENC624J600-I/PT
Manufacturer:
Microchip
Quantity:
3 200
Company:
Part Number:
ENC624J600-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
REGISTER 9-1:
2010 Microchip Technology Inc.
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DMAST: DMA Start bit
1 = DMA is started/busy; automatically cleared by hardware when done
0 = DMA is done/Idle
DMACPY: DMA Copy Control bit
1 = DMA copies data to memory location at EDMADST
0 = DMA does not copy data; EDMADST is ignored
DMACSSD: DMA Checksum Seed Control bit
1 = DMA checksum operations are initially seeded by the one’s complement of the checksum
0 = DMA checksum operations are initially seeded by 0000h
DMANOCS: DMA No Checksum Control bit
1 = DMA does not compute checksums; EDMACS remains unchanged
0 = DMA computes checksums; hardware updates EDMACS at the completion of all DMA operations
TXRTS: Transmit Request to Send Status/Control bit
1 = Transmit an Ethernet frame; automatically cleared by hardware when done
0 = Transmit logic done/Idle
RXEN: Receive Enable bit
1 = Packets which pass the current RX filter configuration are written to the receive buffer
0 = All packets received are ignored
contained in EDMACS
ECON1: ETHERNET CONTROL REGISTER 1 (CONTINUED)
ENC424J600/624J600
DS39935C-page 91