ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 163

• Manufacturer Part Number: ENC624J600-I/PT
• Description: IC ETHERNET CTRLR W/SPI 64-TQFP
• Manufacturer: Microchip Technology

Specifications of ENC624J600-I/PT

• Package / Case: 64-TFQFP
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Registers
Reset
Revision History ................................................................ 157
S
Serial Peripheral Interface (SPI)
SFR. See Special Function Registers................................. 19
SHA-1 Hashing ................................................................. 126
Single Byte Instructions ...................................................... 41
Source Address .................................................................. 72
Special Function Registers ................................................. 19
Speed/Duplex Auto-Negotiation........................................ 109
SPI Instruction Set
 2010 Microchip Technology Inc.
ECON1 (Ethernet Control 1) ....................................... 90
ECON2 (Ethernet Control 2) ....................................... 77
EIDLED (Ethernet ID Status/LED Control).................. 79
EIE (Ethernet Interrupt Enable)................................. 120
EIR (Ethernet Interrupt Flag)..................................... 118
ERXFCON (Ethernet RX Filter Control)...................... 96
ERXWM (Receive Watermark) ................................. 106
ESTAT (Ethernet Status) ............................................ 93
ETXSTAT (Ethernet Transmit Status)......................... 92
MABBIPG (MAC Back-to-Back
MACLCON (MAC Collision Control) ........................... 82
MACON1 (MAC Control 1)........................................ 107
MACON2 (MAC Control 2).......................................... 80
MAIPG (MAC Inter-Packet Gap)................................. 82
MICMD (MII Management Command)........................ 30
MIREGADR (MII Management Address) .................... 29
MISTAT (MII Management Status) ............................. 30
PHANA (PHY Auto-Negotiation
PHANE (PHY Auto-Negotiation Expansion) ............. 115
PHANLPA (PHY Auto-Negotiation Link
PHCON1 (PHY Control 1)......................................... 110
PHCON2 (PHY Control 2)......................................... 139
PHSTAT1 (PHY Status 1)......................................... 111
PHSTAT2 (PHY Status 2)......................................... 112
PHSTAT3 (PHY Status 3)......................................... 112
PHY Subsystem.......................................................... 74
Power-on..................................................................... 73
Receive Only............................................................... 74
System ........................................................................ 73
Transmit Only.............................................................. 74
External Connections.................................................. 14
Instruction Set ............................................................. 39
Physical Implementation ............................................. 39
Address Map
PHY Registers ............................................................ 28
Manual Configuration................................................ 109
N-Byte Instructions
Single Byte Instructions .............................................. 41
Summary Table........................................................... 40
Three-Byte Instructions............................................... 43
Two-Byte Instructions ................................................. 42
Inter-Packet Gap) ............................................... 81
Advertisement).................................................. 113
Partner Ability) .................................................. 114
16-Bit PSP .......................................................... 22
8-Bit PSP ............................................................ 21
SPI ...................................................................... 20
Banked SFR ....................................................... 45
SRAM Buffer ....................................................... 49
Unbanked SFR ................................................... 47
ENC424J600/624J600
SRAM Buffer....................................................................... 32
Start-Of-Frame Delimiter .................................................... 71
Start-of-Stream/Preamble Field .......................................... 71
System Reset ..................................................................... 73
T
Three-Byte Instructions....................................................... 43
Timing Diagrams
Transmit Only Reset ........................................................... 74
Transmitting Packets .................................................... 83–86
Two-Byte Instructions ......................................................... 42
Type/Length Field ............................................................... 72
W
Wake-on-LAN/Remote Wake-up ...................................... 122
WWW Address ................................................................. 162
WWW, On-Line Support ....................................................... 4
Buffer Pointers............................................................ 34
Circular Wrapping
Circular Wrapping with EGPDATA Pointer ................. 35
Direct Access.............................................................. 33
General Purpose Buffer.............................................. 33
Indirect Access ........................................................... 34
Receive Buffer ............................................................ 33
Transmit Buffer ........................................................... 33
N-Byte SPI Instruction
N-Byte SPI Opcode
N-Byte SPI Opcode Instruction
PSP Mode 1 Read...................................................... 54
PSP Mode 1 Write ...................................................... 54
PSP Mode 10 Read.................................................... 70
PSP Mode 10 Write .................................................... 70
PSP Mode 2 Read...................................................... 56
PSP Mode 2 Write ...................................................... 56
PSP Mode 3 Read...................................................... 58
PSP Mode 3 Write ...................................................... 58
PSP Mode 4 Read...................................................... 60
PSP Mode 4 Write ...................................................... 60
PSP Mode 5 Read...................................................... 63
PSP Mode 5 Write ...................................................... 63
PSP Mode 6 Read...................................................... 66
PSP Mode 6 Write ...................................................... 66
PSP Mode 9 Read...................................................... 68
PSP Mode 9 Write ...................................................... 68
Single Byte Instruction................................................ 41
SPI Input................................................................... 146
SPI Output ................................................................ 146
Three-Byte Read Instruction....................................... 43
Three-Byte Write Instruction....................................... 43
Two-Byte Instruction (RBSEL Opcode) ...................... 42
Selecting ETXLEN Values (example) ......................... 84
Special Cases............................................................. 85
Transmission Status ................................................... 85
ERXDATA Pointer .............................................. 36
EUDADATA Pointer...................................... 36–37
(Banked SFR Operations) .................................. 45
(Unbanked SFR Operations) .............................. 47
(SRAM Buffer Operations).................................. 49
DS39935C-page 161