ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 22

• Manufacturer Part Number: ENC624J600-I/PT
• Description: IC ETHERNET CTRLR W/SPI 64-TQFP
• Manufacturer: Microchip Technology

Specifications of ENC624J600-I/PT

• Package / Case: 64-TFQFP
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC424J600/624J600
TABLE 3-1:
DS39935C-page 20
Note 1:
0A
0B
0C
0D
0E
1A
1B
1C
1D
1E
00
01
02
03
04
05
06
07
08
09
0F
10
11
12
13
14
15
16
17
18
19
1F
2:
0A
0B
0C
0D
0E
0F
1A
1B
1C
1D
1E
1F
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
Unbanked SFRs can be accessed only by unbanked SPI opcodes.
When using these registers to access the SRAM buffer, use only the N-byte SRAM instructions. See Section 4.6.2
“Unbanked SFR Operations” and Section 4.6.3 “SRAM Buffer Operations” for more details.
(00h offset)
Bank 0
ERXHEADH
EDMALENH
EDMADSTH
ERXHEADL
EDMALENL
EDMADSTL
ETXWIREH
ETXWIREL
EDMACSH
ETXSTATL
ETXSTATH
EUDANDH
ERXTAILH
EDMASTH
EDMACSL
ETXLENH
ERXTAILL
EDMASTL
EUDASTL
EUDASTH
EUDANDL
ETXLENL
ECON1H
ERXSTH
ECON1L
ETXSTH
ERXSTL
ETXSTL
ESTATH
ESTATL
ENC424J600/624J600 SFR MAP (SPI INTERFACE)
Name
EIRH
EIRL
2A
2B
2C
2D
2E
3A
3B
3C
3D
3E
20
21
22
23
24
25
26
27
28
29
2F
30
31
32
33
34
35
36
37
38
39
3F
(20h offset)
Bank 1
ERXFCONH
ERXFCONL
EUDANDH
EUDASTH
EUDANDL
EUDASTL
EPMM1H
EPMM2H
EPMM3H
EPMM4H
EPMCSH
EPMM1L
EPMM2L
EPMM3L
ECON1H
EPMM4L
EPMCSL
ECON1L
ESTATH
EPMOH
EPMOL
ESTATL
EHT1H
EHT2H
EHT3H
EHT4H
EHT1L
EHT2L
EHT3L
EHT4L
Name
EIRH
EIRL
4C
4D
5C
5D
40
41
42
43
44
45
46
47
48
49
4A
4B
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5E
5F
(40h offset)
Bank 2
MIREGADRH
MIREGADRL
MACLCONH
MACLCONL
MABBIPGH
MABBIPGL
MACON1H
MACON2H
MACON1L
MACON2L
MAMXFLH
EUDANDH
MAMXFLL
EUDASTH
EUDANDL
EUDASTL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MICMDH
ECON1H
MAIPGH
MICMDL
ECON1L
MAIPGL
ESTATH
ESTATL
Name
EIRH
EIRL
6A
6B
6C
6D
6E
7A
7B
7C
7D
7E
60
61
62
63
64
65
66
67
68
69
6F
70
71
72
73
74
75
76
77
78
79
7F
(60h offset)
Bank 3
EUDANDH
MAADR3H
MAADR2H
MAADR1H
EUDASTH
EUDANDL
MAADR3L
MAADR2L
MAADR1L
EUDASTL
ERXWMH
ERXWML
EIDLEDH
MISTATH
ECON2H
EIDLEDL
ECON1H
MISTATL
EPAUSH
ECON1L
EPAUSL
ECON2L
ESTATH
ESTATL
MIWRH
MIWRL
MIRDH
MIRDL
Name
EIEH
EIRH
EIEL
EIRL
 2010 Microchip Technology Inc.
8A
8B
8C
8D
8E
8F
9A
9B
9C
9D
9E
9F
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
Unbanked
(80h offset)
EUDAWRPTH
EUDADATA
EUDAWRPTL
EUDARDPTH
EUDARDPTL
EGPWRPTL
EGPWRPTH
ERXWRPTH
EGPDATA
ERXDATA
EGPRDPTH
ERXRDPTH
ERXWRPTL
EGPRDPTL
ERXRDPTL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Name
—
—
(1)
(2)
(2)
(2)