ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 30

• Manufacturer Part Number: ENC624J600-I/PT
• Description: IC ETHERNET CTRLR W/SPI 64-TQFP
• Manufacturer: Microchip Technology

Specifications of ENC624J600-I/PT

• Package / Case: 64-TFQFP
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC424J600/624J600
3.3
The PHY registers provide configuration and control of
the PHY module, as well as status information about its
operation. These 16-bit registers are located in their
own memory space, outside of the main SFR space.
Unlike other SFRs, the PHY SFRs are not directly
accessible through the SPI or PSP interfaces. Instead,
access is accomplished through a special set of MAC
control registers that implement a Media Independent
Interface Management (MIIM) defined by IEEE 802.3;
these are the MICMD, MISTAT and MIREGADR
registers.
There are a total of 32 PHY addresses; however, only
10 locations implement user-accessible registers listed
in Table 3-8. Writes to unimplemented locations are
ignored and any attempts to read these locations return
FFFFh. Do not write to reserved PHY register locations
and ignore their content if read.
TABLE 3-8:
DS39935C-page 28
Address
0A
0B
0C
0D
0E
0F
00
01
02
03
04
05
06
07
08
09
PHY Special Function Registers
PHANLPA
PHSTAT1
Reserved
Reserved
PHCON1
PHANA
PHANE
Name
PHY SPECIAL FUNCTION
REGISTER MAP
—
—
—
—
—
—
—
—
—
Address
1A
1B
1C
1D
1E
1F
10
11
12
13
14
15
16
17
18
19
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PHSTAT2
Reserved
Reserved
Reserved
PHSTAT3
PHCON2
Name
—
—
—
—
3.3.1
When a PHY register is read, the entire 16 bits are
obtained.
To read from a PHY register:
1.
2.
3.
4.
5.
3.3.2
When a PHY register is written to, the entire 16 bits are
written
implemented. If it is necessary to reprogram only select
bits in the register, the host microcontroller must first
read the PHY register, modify the resulting data and
then write the data back to the PHY register.
To write to a PHY register:
1.
2.
3.
The PHY register is written after the MIIM operation
completes, which takes 25.6 s. When the write opera-
tion has completed, the BUSY bit clears itself. The host
controller should not start any MIISCAN, MIWR or
MIIRD operations while the BUSY bit is set.
Write the address of the PHY register to read
from
(Register 3-1). Make sure to also set reserved
bit 8 of this register.
Set the MIIRD bit (MICMD<0>, Register 3-2).
The read operation begins and the BUSY bit
(MISTAT<0>, Register 3-3) is automatically set
by hardware.
Wait 25.6 s. Poll the BUSY (MISTAT<0>) bit to
be certain that the operation is complete. While
busy, the host controller should not start any
MIISCAN operations or write to the MIWR
register. When the MAC has obtained the register
contents, the BUSY bit will clear itself.
Clear the MIIRD (MICMD<0>) bit.
Read the desired data from the MIRD register.
For 8-bit interfaces, the order that these bytes
are read is unimportant.
Write the address of the PHY register to write to
into the MIREGADR register. Make sure to also
set reserved bit 8 of this register.
Write the 16 bits of data into the MIWR register.
The low byte must be written first, followed by
the high byte.
Writing to the high byte of MIWR begins the
MIIM transaction and the BUSY (MISTAT<0>)
bit is automatically set by hardware.
at
READING PHY REGISTERS
WRITING PHY REGISTERS
into
once;
the
selective
 2010 Microchip Technology Inc.
MIREGADR
bit
writes
register
are
not