ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 15

• Manufacturer Part Number: ENC624J600-I/PT
• Description: IC ETHERNET CTRLR W/SPI 64-TQFP
• Manufacturer: Microchip Technology

Specifications of ENC624J600-I/PT

• Package / Case: 64-TFQFP
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

 2010 Microchip Technology Inc.
2.6
The INT pin is an active-low signal that is used to flag
interrupt events to external devices. Depending on the
application, it can be used to signal the host micro-
controller whenever a packet has been received or
transmitted,
operation has occurred. It can also be used to wake-up
the microcontroller or other system components based
on LAN activity; its use is optional.
The INT pin is driven high when no interrupt is pending
and is driven low when an interrupt has occurred. It
does not go into a high-impedance state, except during
initial power-on while the multiplexed SPISEL pin
function is being used.
Since ENC424J600/624J600 devices incorporate a
buffer for storing transmit and receive packets, the host
microcontroller never needs to perform real-time
operations on the device. The microcontroller can poll
the device registers to discover if the device status has
changed.
2.7
For the maximum degree of flexibility in interfacing with
microcontrollers, ENC424J600/624J600 devices offer
a choice between a serial interface based on the Serial
Peripheral Interface (SPI) standard, and a flexible 8 or
16-bit parallel slave port (PSP) interface. Only one
interface may be used at any given time.
The I/O interface is hardware selected on power-up
using the SPISEL function on the INT/SPISEL pin. This
is done by latching in the voltage level applied to the pin
FIGURE 2-9:
MCU
INT Pin
Host Interface Pins
(internal weak pull-up on CS enabled)
INT0
SDO
SCK
SDI
or
I/O
that
SPI Selected
USING THE INT/SPISEL PIN TO SELECT THE I/O INTERFACE
some
3.3V
100k
other
INT/SPISEL
CS
SCK
SI
SO
ENCX24J600
asynchronous
~2.2V
ENC424J600/624J600
approximately 1 to 10 s after power is applied to the
device and the device exits Power-on Reset. If SPISEL
is latched at a logic high state, the serial interface is
enabled. If SPISEL is latched at a logic low state, the
PSP interface is enabled. Figure 2-9 shows example
connections required to select the SPI or PSP interface
upon power-up.
To ensure the SPI interface is selected upon power-up,
an external pull-up resistor to V
to the SPISEL pin. Alternatively, if the parallel interface
is to be used, a pull-down resistor to V
connected to the SPISEL pin. In most circuits, it is rec-
ommended that a 100 kΩ or smaller resistor be used to
ensure that the correct logic level is latched in reliably.
If a large capacitance is present in the SPISEL circuit,
such as from stray capacitance, a smaller pull-up or
pull-down resistor may be required to compensate and
ensure the correct level is sensed during power-up.
As SPISEL is multiplexed with the INT interrupt output
function, a direct connection to V
resistor is prohibited. If INT is connected to the host
microcontroller, the microcontroller must leave this
signal in a high-impedance state and not attempt to
drive it to an incorrect logic state during power-up.
If the V
exit POR, exceed the 1 to 10 s latch timer and sample
the SPISEL pin state before V
ified minimum operating voltage of the device. In this
case, the device will still latch in the correct value,
assuming the minimum V
(D006) specification is met, which is a function of V
PMAx/PMDx
MCU
(internal weak pull-down on CS enabled)
DD
PMCS2
PMALL
PMWR
RMRD
INT0
supply has a slow ramp rate, the device will
PSP Selected (Mode 5 shown)
100k
IH
DD
(D004) or maximum V
DD
has reached the spec-
DD
must be connected
ADx
DS39935C-page 13
AL
CS
RD
WR
INT/SPISEL
ENCX24J600
or V
SS
SS
without a
V
must be
SS
DD
IL
.