ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 77

• Manufacturer Part Number: ENC624J600-I/PT
• Description: IC ETHERNET CTRLR W/SPI 64-TQFP
• Manufacturer: Microchip Technology

Specifications of ENC624J600-I/PT

• Package / Case: 64-TFQFP
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.0
Before using an ENCX24J600 device to transmit and
receive packets, certain device settings must be initial-
ized. Depending on the application, some configuration
options may be left set to their default values. Those
that need to be changed are typically set once after
power-up and not changed thereafter.
8.1
Because it is possible for the host controller to reset
independently from the ENCX24J600 (for example,
when using an external debugger to reprogram the
host), it is recommended that software issue a System
Reset of the ENCX24J600 as the first step of its
ordinary initialization routine.
Also, since it is possible for the host controller to exit its
POR, begin code execution before the ENCX24J600
exits POR and latches the Interface mode, special care
should be taken in the software to ensure that it does
not attempt to blindly initialize the ENCX24J600
registers before the device is actually out of Reset. To
take care of these potential pitfalls, it is recommended
that
approach to ensure proper start-up. For example:
1.
2.
3.
4.
5.
6.
7.
The ENCX24J600 is now ready to accept further
commands.
8.2
If the ENCX24J600 is providing a system clock for the
host controller, or other hardware features of the
application, it is recommended that the application con-
figure the output frequency on the CLKOUT pin first.
The frequency is set by using the COCON<3:0> bits
(ECON2<11:8>). By default, the output frequency on
CLKOUT after a POR is 4 MHz. The last programmed
frequency is maintained after all other Reset events.
For more information on using the output of the
CLKOUT pin, see Section 2.2 “CLKOUT Pin” .
 2010 Microchip Technology Inc.
Write 1234h to EUDAST.
Read EUDAST to see if it now equals 1234h. If
it does not, the SPI/PSP interface may not be
ready yet, so return to step 1 and try again.
Poll CLKRDY (ESTAT<12>) and wait for it to
become set.
Issue a System Reset command by setting
ETHRST (ECON2<4>).
In software, wait at least 25  s for the Reset to
take place and the SPI/PSP interface to begin
operating again.
Read EUDAST to confirm that the System Reset
took place. EUDAST should have reverted back
to its Reset default of 0000h.
Wait at least 256  s for the PHY registers and
PHY status bits to become available.
firmware
INITIALIZATION
Reset
CLKOUT Frequency
take
a
write-verify-reset-reverify
ENC424J600/624J600
8.3
Before packet reception is enabled, the receive buffer
must be configured by programming the ERXST
Pointer. All memory between this pointer and the end of
the physical memory (5FFFh), including those
addresses, are reserved as the receive buffer for
incoming packets. The value of ERXST must be
word-aligned, since all incoming frames must be stored
beginning at even addresses.
If an application expects a large amount of incoming
traffic or frequent packet delivery, it is recommended
that it allocate a larger receive buffer. Applications
needing more space for saving old packets or other
temporary storage, or wishing to hold several packets
ready for transmission, can allocate less memory for
the receive buffer.
Reception of incoming packets begins at the address
designated by ERXST.
8.4
No specific transmit buffer is defined. The host applica-
tions may write frames to be transmitted to any unused
space in the SRAM buffer; no initialization is necessary.
8.5
Before enabling packet reception, configure the receive
filters to eliminate unwanted incoming packets. See
Section 10.0 “Receive Filters” for details.
8.6
Once the receive buffer and filters are properly
configured, several MAC registers must be configured.
The order of programming is unimportant.
• If flow control operation is desired, configure the
• Verify that the TXCRCEN (MACON2<4>) and
• Program the MAMXFL register with the maximum
• Set the RXEN bit (ECON1<0>) to enable packet
flow control module as described in Section 11.0
“Flow Control” .
PADCFG<2:0> (MACON2<7:5>) bits are set
correctly. Most applications will not need to modify
these settings from their power-on defaults.
frame length to be accepted (received or transmit-
ted). Most network nodes are configured to
handle packets that are 1518 bytes or less
(1522 bytes or less if VLAN tagging is used).
Alternately, set HFRMEN (MACON2<2>) to
accept any size frame.
reception by the MAC.
Receive Buffer
Transmit Buffer
Receive Filters
MAC Initialization
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