ENC624J600-I/PT Microchip Technology, ENC624J600-I/PT Datasheet - Page 141

• Manufacturer Part Number: ENC624J600-I/PT
• Description: IC ETHERNET CTRLR W/SPI 64-TQFP
• Manufacturer: Microchip Technology

Specifications of ENC624J600-I/PT

• Package / Case: 64-TFQFP
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 16-1:
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12
bit 11
bit 10-3
bit 2
bit 1
bit 0
Note 1:
R/W-0
R/W-0
r
r
Intended for testing purposes only. Do not use in 10 Mbps operation.
Reserved: Write as ‘ 0 ’, ignore on read
EDPWRDN: Energy Detect Power-Down Enable bit
1 = Energy detect power-down enabled. PHY automatically powers up and down based on the state
0 = Energy detect power-down disabled. Use this setting for maximal compatibility.
Reserved: Write as ‘ 0 ’, ignore on read
EDTHRES: Energy Detect Threshold Control bit
1 = Less energy is required to wake the PHY from energy detect power-down
0 = Normal energy detect threshold
Reserved: Write as ‘ 0 ’, ignore on read
FRCLNK: Force Link Control bit
1 = Force immediate link up, even when no link partner is present (100 Mbps operation only)
0 = Normal operation
EDSTAT: Energy Detect Status bit
1 = Energy detect circuit has detected energy on the TPIN+/- pins within the last 256 ms
0 = No energy has been detected on the TPIN+/- pins within the last 256 ms
Reserved: Write as ‘ 0 ’, ignore on read
R/W-0
R/W-0
of EDSTAT.
r
r
PHCON2: PHY CONTROL REGISTER 2
W = Writable bit
‘1’ = Bit is set
EDPWRDN
R/W-0
R/W-0
r
R/W-0
R/W-0
r
r
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
EDTHRES
ENC424J600/624J600
R/W-0
R/W-0
r
FRCLNK
R/W-0
R/W-0
r
x = Bit is unknown
EDSTAT
R/W-0
R-1
r
DS39935C-page 139
R/W-0
R/W-0
(1)
r
r
bit 8
bit 0