CYP15G0401RB-BGXC Cypress Semiconductor Corp, CYP15G0401RB-BGXC Datasheet - Page 12

• Manufacturer Part Number: CYP15G0401RB-BGXC
• Description: IC RECEIVER HOTLINK 256LBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink II™r
• Type: Transceiverr

Specifications of CYP15G0401RB-BGXC

• Package / Case: 256-LBGA Exposed Pad, 32-HLBGA
• Number Of Drivers/receivers: 0/4
• Protocol: Multiprotocol
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Product: PHY
• Data Rate: 1500 MBd
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current: 0.69 A
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 4RX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 38-02111 Rev. **
Table 3. Operating Speed Settings
The TRGCLK± input is a differential input with each input inter-
nally biased to 1.4V. If the TRGCLK+ input is connected to a
TTL, LVTTL, or LVCMOS clock source, TRGCLK– can be left
floating and the input signal is recognized when it passes
through the internally biased reference point.
When both the TRGCLK+ and TRGCLK– inputs are
connected, the clock source must be a differential clock. This
can be either a differential LVPECL clock that is DC- or
AC-coupled, or a differential LVTTL or LVCMOS clock.
By connecting the TRGCLK– input to an external voltage
source or resistive voltage divider, it is possible to adjust the
reference point of the TRGCLK+ input for alternate logic
levels. When doing so, it is necessary to ensure that the input
differential crossing point remains within the parametric range
supported by the input.
Clock/Data Recovery
The extraction of a bit-rate clock and recovery of bits from each
received serial stream is performed by a separate Clock/Data
Recovery (CDR) block within each receive channel. The clock
extraction function is performed by embedded phase-locked
loops (PLLs) that track the frequency of the transitions in the
incoming bit streams and align the phase of their internal
bit-rate clocks to the transitions in the selected serial data
streams.
Each CDR accepts a character-rate (bit-rate
half-character-rate (bit-rate
TRGCLK input. This TRGCLK input is used to
Regardless of the type of signal present, the CDR will attempt
to recover a data stream from it. If the frequency of the
recovered data stream is outside the limits of the range control
monitor, the CDR will switch to track TRGCLK instead of the
data stream. Once the CDR output (RXCLKx) frequency
returns back close to TRGCLK frequency, the CDR input will
be switched back to track the input data stream. In case no
data is present at the input this switching behavior may result
in brief RXCLKx frequency excursions from TRGCLK.
However, the validity of the input data stream is indicated by
Notes:
• ensure that the VCO (within the CDR) is operating at the
• to reduce PLL acquisition time
• and to limit unlocked frequency excursions of the CDR VCO
7. The standard definition of a Comma contains only seven bits. However, since all valid Comma characters within the 8B/10B character set also have the eighth
8. When Receive BIST is enabled on a channel, the Low-Latency Framer must not be enabled. The BIST sequence contains an aliased K28.5 framing character,
MID (Open)
SPDSEL
correct frequency.
when there is no input data present at the selected Serial
Line Receiver.
bit as an inversion of the seventh bit, the compare pattern is extended to a full eight bits to reduce the possibility of a framing error.
which would cause the Receiver to update its character boundaries incorrectly.
HIGH
LOW
TRGRATE
1
0
1
0
1
0
÷
20) training clock from the
Frequency
TRGCLK
reserved
19.5–40
80–150
20–40
40–75
(MHz)
40–80
Rate (MBaud)
Signaling
800–1500
195–400
400–800
PRELIMINARY
÷
10) or
the LFIx output. The frequency of TRGCLK is required to be
within ±1500 ppm
the TRGCLK input of the remote transmitter to ensure a lock
to the incoming data stream.
For systems using multiple or redundant connections, the LFIx
output can be used to select an alternate data stream. When
an LFIx indication is detected, external logic can toggle
selection of the associated INx1± and INx2± inputs through the
associated INSELx input. When a port switch takes place, it is
necessary for the receive PLL for that channel to reacquire the
new serial stream and frame to the incoming character bound-
aries.
Deserializer/Framer
Each CDR circuit extracts bits from the associated serial data
stream and clocks these bits into the Shifter/Framer at the
bit-clock rate. When enabled, the Framer examines the data
stream, looking for one or more Comma or K28.5 characters
at all possible bit positions. The location of this character in the
data stream is used to determine the character boundaries of
all following characters.
Framing Character
The CYP15G0401RB allows selection of two combinations of
framing characters to support requirements of different inter-
faces. The selection of the framing character is made through
the FRAMCHAR input.
The specific bit combinations of these framing characters are
listed in Table 4. When the specific bit combination of the
selected framing character is detected by the Framer, the
boundaries of the characters present in the received data
stream are known.
Table 4. Framing Character Selector
Framer
The Framer on each channel operates in one of three different
modes, as selected by the RFMODE input. In addition, the
Framer itself may be enabled or disabled through the RFEN
input. When RFEN = LOW, the framers in all four receive paths
are disabled, and no combination of bits in a received data
stream will alter the character boundaries. When RFEN
= HIGH, the Framer selected by RFMODE is enabled on all
four channels.
When
selected
character clock until it aligns with the received character
boundaries. In this mode, the Framer starts its alignment
process on the first detection of the selected framing
FRAMCHAR
MID (Open)
HIGH
LOW
RFMODE = LOW,
[8]
. This Framer operates by stretching the recovered
[4]
Character Name
of the frequency of the clock that drives
or Comma−
or +K28.5
Comma+
–K28.5
Bits Detected in Framer
the
Reserved for test
CYP15G0401RB
Low-Latency
or 11000001XX
00111110XX
0011111010 or
Bits Detected
1100000101
Page 12 of 35
Framer
[7]
is
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