CYP15G0401RB-BGXC Cypress Semiconductor Corp, CYP15G0401RB-BGXC Datasheet - Page 8

• Manufacturer Part Number: CYP15G0401RB-BGXC
• Description: IC RECEIVER HOTLINK 256LBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink II™r
• Type: Transceiverr

Specifications of CYP15G0401RB-BGXC

• Package / Case: 256-LBGA Exposed Pad, 32-HLBGA
• Number Of Drivers/receivers: 0/4
• Protocol: Multiprotocol
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Product: PHY
• Data Rate: 1500 MBd
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current: 0.69 A
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 4RX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 38-02111 Rev. **
Pin Descriptions
CYP15G0401RB Quad HOTLink II Receiver
RXCLKA±
RXCLKB±
RXCLKC±
RXCLKD±
RXCKSEL Three-level Select
DECMOD
E
RFMODE Three-level Select
Pin Name
Three-state, LVTTL
Output clock or static
control input
static control input
Three-level Select
static control input
static control input
I/O Characteristics
(continued)
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,
,
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Receive Character Clock Output or Clock Select Input. When configured such that all
output data paths are clocked by the recovered clock (RXCKSEL = MID), these true and
complement clocks are the receive interface clocks which are used to control timing of
output data (RXDx[7:0], RXSTx[2:0] and RXOPx). These clocks are output continuously
at either the dual-character rate (1/20
serial bit-rate) of the data being received, as selected by RXRATE.
When configured such that all output data paths are clocked by TRGCLK instead of a
recovered clock (RXCKSEL = LOW), the RXCLKA± and RXCLKC± output drivers present
a buffered and delayed form of TRGCLK. RXCLKA± and RXCLKC± are buffered forms
of TRGCLK that are slightly different in phase. This phase difference allows the user to
select the optimal setup/hold timing for their specific interface.
Receive Clock Mode. Selects the receive clock source used to transfer data to the
Output Registers.
When LOW, all four Output Registers are clocked by TRGCLK. RXCLKB± and RXCLKD±
outputs are disabled (High-Z), and RXCLKA± and RXCLKC± present buffered and
delayed forms of TRGCLK.
When MID, each RXCLKx± output follows the recovered clock for the respective channel,
as selected by RXRATE. When the 10B/8B Decoder and Elasticity Buffer are bypassed
(DECMODE = LOW), RXCKSEL must be MID.
When HIGH and the receive channels are operated in independent mode (RX modes 0
and 2), RXCLKA± and RXCLKC± output the recovered clock from receive channel A, B,
C, or D, as selected by RXCLKB+ and RXCLKD+. This output clock may operate at the
character-rate or half the character-rate as selected by RXRATE.
Decoder Mode Select. This input selects the behavior of the Decoder block. When LOW,
the Decoder is bypassed and raw 10-bit characters are passed to the Output Register.
When the Decoder is bypassed, RXCKSEL must be MID.
When MID, the Decoder is enabled and the Cypress decoder table for Special Code
characters is used.
When HIGH, the Decoder is enabled and the alternate decoder table for Special Code
characters is used. See Table 15 for a list of the Special Codes supported in both encoded
modes.
Reframe Mode Select. Used to select the type of character framing used to adjust the
character boundaries (based on detection of one or more framing characters in the
received serial bit stream). This signal operates with the type of framing character
selected.
When LOW, the Low-Latency Framer is selected. This will frame on each occurrence of
the selected framing character(s) in the received data stream. This mode of framing
stretches the recovered character-rate clock for one or multiple cycles to align that clock
with the recovered data.
When MID, the Cypress-mode Multi-Byte parallel Framer is selected. This requires a pair
of the selected framing character(s), on identical 10-bit boundaries, within a span of 50
bits, before the character boundaries are adjusted. The recovered character clock
remains in the same phase regardless of character offset.
When HIGH, the alternate mode Multi-Byte parallel Framer is selected. This requires
detection of the selected framing character(s) of the allowed disparities in the received
serial bit stream, on identical 10-bit boundaries, on four directly adjacent characters. The
recovered character clock remains in the same phase regardless of character offset.
PRELIMINARY
Signal Description
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the serial bit-rate) or character rate (1/10
CYP15G0401RB
Page 8 of 35
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the
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