CYP15G0401RB-BGXC Cypress Semiconductor Corp, CYP15G0401RB-BGXC Datasheet - Page 22

• Manufacturer Part Number: CYP15G0401RB-BGXC
• Description: IC RECEIVER HOTLINK 256LBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink II™r
• Type: Transceiverr

Specifications of CYP15G0401RB-BGXC

• Package / Case: 256-LBGA Exposed Pad, 32-HLBGA
• Number Of Drivers/receivers: 0/4
• Protocol: Multiprotocol
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Product: PHY
• Data Rate: 1500 MBd
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current: 0.69 A
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 4RX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 38-02111 Rev. **
CYP15G0401RB AC Characteristics
Capacitance
t
t
CYP15G0401RB TRGCLK Switching Characteristics Over the Operating Range
f
t
t
t
t
t
t
t
t
t
t
t
t
t
CYP15G0401RB Receive Serial Inputs and CDR PLL Characteristics Over the Operating Range
t
t
t
t
C
C
Notes:
22. The ratio of rise time to falling time must not vary by greater than 2:1.
23. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.
24. Parallel data output specifications are only valid if all inputs or outputs are loaded with similar DC and AC loads.
25. The duty cycle specification is a simultaneous condition with the t
26. Since this timing parameter is greater than the minimum time period of TRGCLK it sets an upper limit to the frequency in which TRGCLKx can be used to clock
27. Total jitter is calculated at an assumed BER of 1E –12. Hence: total jitter (t
28. Also meets all Jitter Tolerance requirements as specified by OBSAI RP3, CPRI, ESCON, FICON, Fibre Channel and DVB-ASI.
29. Receiver UI (Unit Interval) is calculated as 1/(f
RXDV–
RXDV+
TRG
TRGCLK
TRGH
TRGL
TRGD
TRGR
TRGF
RTRGDA
RTRGDV
TRGADV–
TRGADV+
TRGCDV–
TRGCDV+
TRGRX
RXLOCK
RXUNLOCK
JTOL
DJTOL
INTTL
INPECL
Parameter
cannot be as large as 30% – 70%.
the receive data out of the output register. For predictable timing, users can use this parameter only if TRGCLK period is greater than sum of t
set-up time of the upstream device. When this condition is not true, RXCLKC± or RXCLKA± (a buffered or delayed version of TRGCLK when RXCKSELx =
LOW) could be used to clock the receive data out of the device.
* 20) (when RXRATE = HIGH) or 1/(f
to t
Parameter
[27]
B
[21, 22, 23]
[25]
[21, 22, 23]
[27 ]
.
[24]
[4]
[24]
[26]
[21]
Status and Data Valid Time to RXCLKx (RXCKSEL HIGH or MID)
Status and Data Valid Time to RXCLKx (HALF RATE RECOVERED
CLOCK)
Status and Data Valid Time From RXCLKx (RXCKSEL HIGH or MID)
Status and Data Valid Time From RXCLKx (HALF RATE RECOVERED
CLOCK)
TRGCLK Clock Frequency
TRGCLK Period
TRGCLK HIGH Time (TRGRATE = HIGH)
TRGCLK HIGH Time (TRGRATE = LOW)
TRGCLK LOW Time (TRGRATE = HIGH)
TRGCLK LOW Time (TRGRATE = LOW)
TRGCLK Duty Cycle
TRGCLK Rise Time (20% – 80%)
TRGCLK Fall Time (20% – 80%)
Receive Data Access Time from TRGCLK (RXCKSEL = LOW)
Receive Data Valid Time from TRGCLK (RXCKSEL = LOW)
Received Data Valid Time to RXCLKA (RXCKSEL = LOW)
Received Data Valid Time from RXCLKA (RXCKSEL = LOW)
Received Data Valid Time to RXCLKC (RXCKSEL = LOW)
Received Data Valid Time from RXCLKC (RXCKSEL = LOW)
TRGCLK Frequency Referenced to Received Clock Period
Receive PLL lock to input data stream (cold start)
Receive PLL lock to input data stream
Receive PLL Unlock Rate
Total Jitter Tolerance
Deterministic Jitter Tolerance
TTL Input Capacitance
PECL input Capacitance
TRG
Description
* 10) (when RXRATE = LOW) of the remote transmitter if data is being received. In an operating link this is equivalent
TRG
* 20) (when RXRATE = HIGH) or 1/(f
Over the Operating Range (continued)
Description
PRELIMINARY
TRGH
T
T
and t
A
A
= 25°C, f
= 25°C, f
J
TRGL
) = (t
RJ
parameters. This means that at faster character rates the TRGCLK duty cycle
* 14) + t
0
0
Test Conditions
= 1 MHz, V
= 1 MHz, V
TRG
IEEE 802.3z
IEEE 802.3z
* 10) (when RXRATE = LOW) if no data is being received, or 1/(f
DJ
.
CC
CC
= 3.3V
= 3.3V
[28]
[28]
10UI – 4.7
10UI – 4.3
5UI – 1.5
5UI – 1.0
5UI – 1.8
5UI – 2.3
2.9
2.9
–1500
Min.
19.5
6.66
–0.2
600
370
5.9
5.9
2.5
0.5
30
CYP15G0401RB
[21]
[21]
Max.
7
4
+1500
51.28
Max.
376K
376K
150
9.5
70
46
Page 22 of 35
2
2
RTRGDA
Unit
pF
pF
and
UI
MHz
Unit
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UI
UI
ps
ps
TRG
%
[29]
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