PIC24HJ128GP510-I/PT Microchip Technology Inc., PIC24HJ128GP510-I/PT Datasheet - Page 132

• Manufacturer Part Number: PIC24HJ128GP510-I/PT
• Description: MCU, 16-Bit, 128KB Flash, 8KB RAM, 85 I/O, TQFP-100
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24HJ128GP510-I/PT

• A/d Inputs: 32 Channel, 12-Bit
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 85
• Interface: CAN/I2C/SPI/UART
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Inputs: 85
• Number Of Pins: 100
• Package Type: 100-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 8K Bytes
• Speed: 40 MIPS
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6 V
• Voltage, Rating: 3-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC24HJXXXGPX06/X08/X10
10.2
In addition to the PORT, LAT and TRIS registers for
data control, each port pin can also be individually
configured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits con-
figures the corresponding pin to act as an open-drain
output.
The open-drain feature allows the generation of
outputs higher than V
tal only pins by using external pull-up resistors. (The
open-drain I/O feature is not supported on pins that
have analog functionality multiplexed on the pin.) The
maximum open-drain voltage allowed is the same as
the maximum V
feature is supported for both port pin and peripheral
configurations.
10.3
The use of the ADxPCFGH, ADxPCFGL and TRIS
registers control the operation of the A/D port pins. The
port pins that are desired as analog inputs must have
their corresponding TRIS bit set (input). If the TRIS bit
is cleared (output), the digital output level (V
is converted.
Clearing any bit in the ADxPCFGH or ADxPCFGL reg-
ister configures the corresponding bit to be an analog
pin. This is also the Reset state of any I/O pin that has
an analog (ANx) function associated with it.
When reading the PORT register, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin that is defined as
a digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
EXAMPLE 10-1:
DS70175F-page 130
Note:
Note:
MOV
MOV
NOP
btss
Open-Drain Configuration
Configuring Analog Port Pins
0xFF00, W0
W0, TRISBB
PORTB, #13
In devices with two A/D modules, if the
corresponding
AD1PCFGH(L) and AD2PCFGH(L) is
cleared, the pin is configured as an analog
input.
The voltage on an analog input pin can be
between -0.3V to (V
IH
specification. The open-drain output
DD
PORT WRITE/READ EXAMPLE
(e.g., 5V) on any desired digi-
PCFG
DD
; Configure PORTB<15:8> as inputs
; and PORTB<7:0> as outputs
; Delay 1 cycle
; Next Instruction
+ 0.3 V).
bit
in
OH
or V
either
OL
)
10.4
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically, this instruction
would be a NOP.
10.5
The input change notification function of the I/O ports
allows the PIC24HJXXXGPX06/X08/X10 devices to
generate interrupt requests to the processor in
response to a change-of-state on selected input pins.
This
change-of-states even in Sleep mode, when the clocks
are disabled. Depending on the device pin count, there
are up to 24 external signals (CN0 through CN23) that
can be selected (enabled) for generating an interrupt
request on a change-of-state.
There are four control registers associated with the CN
module. The CNEN1 and CNEN2 registers contain the
CN interrupt enable (CNxIE) control bits for each of the
CN input pins. Setting any of these bits enables a CN
interrupt for the corresponding pins.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source that is connected
to the pin and eliminate the need for external resistors
when push button or keypad devices are connected.
The pull-ups are enabled separately using the CNPU1
and CNPU2 registers, which contain the weak pull-up
enable (CNxPUE) bits for each of the CN pins. Setting
any of the control bits enables the weak pull-ups for the
corresponding pins.
Note:
feature
I/O Port Write/Read Timing
Input Change Notification
Pull-ups on change notification pins
should always be disabled whenever the
port pin is configured as a digital output.
is
capable
© 2007 Microchip Technology Inc.
of
detecting
input