PIC24HJ128GP510-I/PT Microchip Technology Inc., PIC24HJ128GP510-I/PT Datasheet - Page 87

• Manufacturer Part Number: PIC24HJ128GP510-I/PT
• Description: MCU, 16-Bit, 128KB Flash, 8KB RAM, 85 I/O, TQFP-100
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24HJ128GP510-I/PT

• A/d Inputs: 32 Channel, 12-Bit
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 85
• Interface: CAN/I2C/SPI/UART
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Inputs: 85
• Number Of Pins: 100
• Package Type: 100-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 8K Bytes
• Speed: 40 MIPS
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6 V
• Voltage, Rating: 3-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

REGISTER 6-12:
© 2007 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
R/W-0
R/W-0
IC5IE
T6IE
T6IE: Timer6 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
DMA4IE: DMA Channel 4 Data Transfer Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Unimplemented: Read as ‘0’
OC8IE: Output Compare Channel 8 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
OC7IE: Output Compare Channel 7 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
OC6IE: Output Compare Channel 6 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
OC5IE: Output Compare Channel 5 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
IC6IE: Input Capture Channel 6 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
IC5IE: Input Capture Channel 5 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
IC4IE: Input Capture Channel 4 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
IC3IE: Input Capture Channel 3 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
DMA3IE: DMA Channel 3 Data Transfer Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
C1IE: ECAN1 Event Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
DMA4IE
R/W-0
R/W-0
IC4IE
IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
W = Writable bit
‘1’ = Bit is set
R/W-0
IC3IE
U-0
—
PIC24HJXXXGPX06/X08/X10
DMA3IE
OC8IE
R/W-0
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
OC7IE
R/W-0
R/W-0
C1IE
C1RXIE
OC6IE
R/W-0
R/W-0
x = Bit is unknown
SPI2IE
OC5IE
R/W-0
R/W-0
DS70175F-page 85
SPI2EIE
R/W-0
R/W-0
IC6IE
bit 8
bit 0