PIC24HJ128GP510-I/PT Microchip Technology Inc., PIC24HJ128GP510-I/PT Datasheet - Page 36

• Manufacturer Part Number: PIC24HJ128GP510-I/PT
• Description: MCU, 16-Bit, 128KB Flash, 8KB RAM, 85 I/O, TQFP-100
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24HJ128GP510-I/PT

• A/d Inputs: 32 Channel, 12-Bit
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 85
• Interface: CAN/I2C/SPI/UART
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Inputs: 85
• Number Of Pins: 100
• Package Type: 100-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 8K Bytes
• Speed: 40 MIPS
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6 V
• Voltage, Rating: 3-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 3-7:
TABLE 3-8:
TABLE 3-9:
I2C1RCV
I2C1TRN
I2C1BRG
I2C1ON
I2C1STAT
I2C1ADD
I2C1MSK
Legend:
I2C2RCV
I2C2TRN
I2C2BRG
I2C2CON
I2C2STAT
I2C2ADD
I2C2MSK
Legend:
SFR Name
U1MODE
U1STA
U1TXREG
U1RXREG
U1BRG
Legend:
SFR Name
SFR Name
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0220
0222
0224
0226
0228
SFR
Addr
0200
0202
0204
0206
0208
020A
020C
Addr
021A
021C
SFR
SFR
0210
0212
0214
0216
0218
I2C1 REGISTER MAP
I2C2 REGISTER MAP
UART1 REGISTER MAP
UTXISEL1
UARTEN
Bit 15
ACKSTAT
ACKSTAT
Bit 15
I2CEN
Bit 15
I2CEN
—
—
—
—
—
—
—
—
—
—
—
—
UTXINV UTXISEL0
Bit 14
TRSTAT
TRSTAT
—
—
—
Bit 14
Bit 14
—
—
—
—
—
—
—
—
—
—
—
—
Bit 13
USIDL
I2CSIDL
I2CSIDL
Bit 13
Bit 13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 12
SCLREL
IREN
SCLREL
Bit 12
Bit 12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXBRK
RTSMD
Bit 11
IPMIEN
IPMIEN
Bit 11
Bit 11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXEN
Bit 10
Bit 10
A10M
—
—
—
Bit 10
A10M
BCL
BCL
—
—
—
—
—
—
—
—
—
—
UTXBF
UEN1
Bit 9
DISSLW
GCSTAT
DISSLW
GCSTAT
—
—
Bit 9
Bit 9
—
—
—
Baud Rate Generator Prescaler
—
—
—
UEN0
TRMT
Bit 8
ADD10
SMEN
ADD10
Bit 8
SMEN
Bit 8
—
—
—
—
WAKE
Bit 7
URXISEL<1:0>
IWCOL
GCEN
IWCOL
GCEN
Bit 7
Bit 7
LPBACK
STREN
Bit 6
STREN
I2COV
I2COV
Bit 6
Bit 6
Address Mask Register
Address Mask Register
ABAUD
ADDEN
ACKDT
ACKDT
Baud Rate Generator Register
Bit 5
Baud Rate Generator Register
Bit 5
Address Register
Address Register
UART Transmit Register
Bit 5
D_A
UART Receive Register
D_A
URXINV
RIDLE
ACKEN
ACKEN
Bit 4
Transmit Register
Transmit Register
Receive Register
Bit 4
Receive Register
Bit 4
P
P
BRGH
PERR
RCEN
Bit 3
RCEN
Bit 3
Bit 3
S
S
FERR
Bit 2
Bit 2
R_W
Bit 2
R_W
PEN
PEN
PDSEL<1:0>
OERR
Bit 1
RSEN
RSEN
Bit 1
Bit 1
RBF
RBF
URXDA
STSEL
Bit 0
Bit 0
SEN
Bit 0
TBF
SEN
TBF
Resets
Resets
Resets
0000
0110
xxxx
0000
0000
0000
00FF
0000
1000
0000
0000
0000
0000
00FF
0000
1000
0000
0000
0000
All
All
All