PIC24HJ128GP510-I/PT Microchip Technology Inc., PIC24HJ128GP510-I/PT Datasheet - Page 277

• Manufacturer Part Number: PIC24HJ128GP510-I/PT
• Description: MCU, 16-Bit, 128KB Flash, 8KB RAM, 85 I/O, TQFP-100
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24HJ128GP510-I/PT

• A/d Inputs: 32 Channel, 12-Bit
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 85
• Interface: CAN/I2C/SPI/UART
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Inputs: 85
• Number Of Pins: 100
• Package Type: 100-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 8K Bytes
• Speed: 40 MIPS
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6 V
• Voltage, Rating: 3-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

APPENDIX A:
Revision A (February 2006)
• Initial release of this document
Revision B (March 2006)
• Updated the Configuration Bits Description table
• Updated registers and register maps
• Updated Section 15.0 “Serial Peripheral Interface
• Updated Section 23.0 “Electrical Characteristics”
• Updated pinout diagrams
• Additional minor corrections throughout document
Revision C (May 2006)
• Updated Section 23.0 “Electrical Characteristics”
• Updated the Configuration Bits Description table
• Additional minor corrections throughout document
Revision D (July 2006)
• Added FBS and FSS Device Configuration regis-
• Added INTTREG Interrupt Control and Status
• Added Core Registers BSRAM and SSRAM (see
• Clarified Fail-Safe Clock Monitor operation (see
• Updated COSC<2:0> and NOSC<2:0> bit config-
• Updated CLKDIV register bit configurations (see
• Added Word Write Cycle Time parameter (T
• Noted exceptions to Absolute Maximum Ratings
• Added ADC2 Event Trigger for Timer4/5
• Corrected mislabeled I2COV bit in I2CxSTAT
• Removed AD26a, AD27a, AD28a, AD26b, AD27b
• Revised Table 23-36 (AD63)
© 2007 Microchip Technology Inc.
(Table 20.1)
(SPI)”
text
(Table 20.1)
text
ters (see Table 20-1) and corresponding bit field
descriptions (see Table 20-2). These added regis-
ters replaced the former RESERVED1 and
RESERVED2 registers.
register. (See Section 6.3 “Interrupt Control
and Status Registers”. See also Register 6-33.)
Section 3.2.7 “Data Ram Protection Feature”)
Section 8.3 “Fail-Safe Clock Monitor (FSCM)”)
urations in OSCCON register (see Register 8-1)
Register 8-2)
to Program Flash Memory (see Table 23-12)
on I/O pin output current (see Section 23.0
“Electrical Characteristics”)
(Section 12.0 “Timer2/3, Timer4/5, Timer6/7
and Timer8/9”)
register (see Register 16-2)
and AD28b from Table 23-34 (A/D Module)
REVISION HISTORY
PIC24HJXXXGPX06/X08/X10
WW
)
Revision E (June 2007)
• Updated Section 23.0 “Electrical Characteristics”
• Additional minor corrections throughout document
text
DS70175F-page 275