PIC24HJ128GP510-I/PT Microchip Technology Inc., PIC24HJ128GP510-I/PT Datasheet - Page 200

• Manufacturer Part Number: PIC24HJ128GP510-I/PT
• Description: MCU, 16-Bit, 128KB Flash, 8KB RAM, 85 I/O, TQFP-100
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24HJ128GP510-I/PT

• A/d Inputs: 32 Channel, 12-Bit
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 85
• Interface: CAN/I2C/SPI/UART
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Inputs: 85
• Number Of Pins: 100
• Package Type: 100-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 8K Bytes
• Speed: 40 MIPS
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6 V
• Voltage, Rating: 3-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC24HJXXXGPX06/X08/X10
REGISTER 18-28: CiTRBnDLC: ECAN MODULE BUFFER n DATA LENGTH CONTROL
REGISTER 18-29: CiTRBnDm: ECAN MODULE BUFFER n DATA FIELD BYTE m
DS70175F-page 198
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-10
bit 9
bit 8
bit 7-5
bit 4
bit 3-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
TRBnDm7
R/W-x
R/W-x
EID5
U-0
—
The Most Significant Byte contains byte (m + 1) of the buffer.
EID<5:0>: Extended Identifier bits
RTR: Remote Transmission Request bit
1 = Message will request remote transmission
0 = Normal message
RB1: Reserved Bit 1
User must set this bit to ‘0’ per CAN protocol.
Unimplemented: Read as ‘0’
RB0: Reserved Bit 0
User must set this bit to ‘0’ per CAN protocol.
DLC<3:0>: Data Length Code bits
TRnDm<7:0>: Data Field Buffer ‘n’ Byte ‘m’ bits
TRBnDm6
R/W-x
R/W-x
EID4
U-0
—
(n = 0, 1, ..., 31)
(n = 0, 1, ..., 31; m = 0, 1, ..., 7)
W = Writable bit
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
TRBnDm5
R/W-x
R/W-x
EID3
U-0
—
TRBnDm4
R/W-x
R/W-x
R/W-x
EID2
RB0
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TRBnDm3
R/W-x
R/W-x
R/W-x
DLC3
EID1
TRBnDm2
R/W-x
R/W-x
R/W-x
DLC2
EID0
© 2007 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
TRBnDm1
R/W-x
R/W-x
R/W-x
DLC1
RTR
TRBnDm0
R/W-x
R/W-x
R/W-x
DLC0
RB1
bit 8
bit 0
bit 0