PIC24HJ128GP510-I/PT Microchip Technology Inc., PIC24HJ128GP510-I/PT Datasheet - Page 148

• Manufacturer Part Number: PIC24HJ128GP510-I/PT
• Description: MCU, 16-Bit, 128KB Flash, 8KB RAM, 85 I/O, TQFP-100
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24HJ128GP510-I/PT

• A/d Inputs: 32 Channel, 12-Bit
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 85
• Interface: CAN/I2C/SPI/UART
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Inputs: 85
• Number Of Pins: 100
• Package Type: 100-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 8K Bytes
• Speed: 40 MIPS
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6 V
• Voltage, Rating: 3-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC24HJXXXGPX06/X08/X10
To set up the SPI module for the Slave mode of operation:
1.
2.
3.
4.
FIGURE 15-1:
DS70175F-page 146
Clear the SPIxBUF register.
If using interrupts:
a)
b)
c)
Write the desired settings to the SPIxCON1 and
SPIxCON2
(SPIxCON1<5>) = 0.
Clear the SMP bit.
SDOx
SCKx
SDIx
SSx
Clear the SPIxIF bit in the respective IFSn
register.
Set the SPIxIE bit in the respective IECn
register.
Write the SPIxIP bits in the respective IPCn
register to set the interrupt priority.
Read SPIxBUF
Control
Sync
Transfer
registers
SPI MODULE BLOCK DIAGRAM
SPIxRXB
bit 0
SPIxBUF
SPIxSR
with
Control
Clock
Shift Control
SPIxTXB
MSTEN
Transfer
Write SPIxBUF
Select
Edge
5.
6.
7.
The SPI module generates an interrupt indicating com-
pletion of a byte or word transfer, as well as a separate
interrupt for all SPI error conditions.
16
Note:
If the CKE bit is set, then the SSEN bit
(SPIxCON1<7>) must be set to enable the SSx
pin.
Clear the SPIROV bit (SPIxSTAT<6>).
Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
Secondary
1:1 to 1:8
Prescaler
Internal Data Bus
Both SPI1 and SPI2 can trigger a DMA
data transfer. If SPI1 or SPI2 is selected
as the DMA IRQ source, a DMA transfer
occurs when the SPI1IF or SPI2IF bit gets
set as a result of an SPI1 or SPI2 byte or
word transfer.
1:1/4/16/64
Prescaler
Primary
© 2007 Microchip Technology Inc.
F
SPIxCON1<1:0>
SPIxCON1<4:2>
Enable
Master Clock
CY