SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 105

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 106. Debug register (address 0212h) bit allocation
Table 107. DcInterruptEnable - Device Controller Interrupt Enable register (address 0214h) bit allocation
[1]
SAF1761_1
Product data sheet
Bit
15 to 1
0
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
The reserved bits should always be written with the reset value.
Symbol
-
DEBUG
10.3.5 DcInterruptEnable register
IEVBUS
IEP6TX
IEP2TX
R/W
R/W
R/W
R/W
31
23
15
0
0
0
0
0
0
7
0
0
This register enables or disables individual interrupt sources. The interrupt for each
endpoint can individually be controlled through the associated IEPnRX or IEPnTX bits,
here n represents the endpoint number. All interrupts can globally be disabled through
bit GLINTENA in the Mode register (see
An interrupt is generated when the USB SIE receives or generates an ACK or NAK on the
USB bus. The interrupt generation depends on Debug mode settings of bit fields
CDBGMOD[1:0], DDBGMODIN[1:0] and DDBGMODOUT[1:0]. All data IN transactions
use the Transmit buffers (TX) that are handled by DDBGMODIN bits. All data OUT
transactions go through the Receive buffers (RX) that are handled by DDBGMODOUT
bits. Transactions on control endpoint 0 (IN, OUT and SETUP) are handled by
CDBGMOD bits.
Interrupts caused by events on the USB bus (SOF, suspend, resume, bus reset, set up
and high-speed status) can also be individually controlled. A bus reset disables all
enabled interrupts, except bit IEBRST (bus reset) that remains unchanged.
The DcInterruptEnable register consists of 4 bytes. The bit allocation is given in
Description
reserved
Always set this bit to logic 0 in both 16-bit and 32-bit accesses.
IEP6RX
IEP2RX
IEDMA
R/W
R/W
R/W
R/W
30
22
14
0
0
0
0
0
0
6
0
0
IEHS_STA
IEP5TX
IEP1TX
R/W
R/W
R/W
R/W
29
21
13
0
0
0
0
0
0
5
0
0
Rev. 01 — 18 November 2009
reserved
IERESM
IEP5RX
IEP1RX
[1]
R/W
R/W
R/W
R/W
28
20
12
0
0
0
0
0
0
4
0
0
Table
IESUSP
IEP4TX
IEP0TX
R/W
R/W
R/W
R/W
27
19
11
0
0
0
0
0
0
3
0
0
100).
IEP0RX
IEPSOF
IEP4RX
R/W
R/W
R/W
R/W
10
26
18
0
0
0
0
0
0
2
0
0
Hi-Speed USB OTG controller
reserved
IEP7TX
IEP3TX
IESOF
R/W
R/W
R/W
R/W
25
17
9
0
0
0
0
0
0
1
0
0
SAF1761
© NXP B.V. 2009. All rights reserved.
[1]
IEP0SETUP
unchanged
IEP7RX
IEP3RX
IEBRST
Table
R/W
R/W
R/W
R/W
105 of 166
24
16
0
0
0
0
8
0
0
0
1
107.