SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 118

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 133. DMA Interrupt Reason register (address 0250h) bit allocation
[1]
Table 134. DMA Interrupt Reason register (address 0250h) bit description
Table 135. Internal EOT-functional relation with the DMA_XFER_OK bit
SAF1761_1
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
15 to 13
12
11
10
9
8
7 to 0
INT_EOT DMA_XFER_OK
1
1
0
The reserved bits should always be written with the reset value.
Symbol
-
GDMA_STOP
-
INT_EOT
-
DMA_XFER_OK
-
0
1
1
10.5.6 DMA Interrupt Reason register
R/W
R/W
15
0
0
7
0
0
This 2-byte register shows the source(s) of DMA interrupt. Each bit is refreshed after a
DMA command is executed. An interrupt source is cleared by writing logic 1 to the
corresponding bit. On detecting the interrupt, the external microprocessor must read the
DMA Interrupt Reason register and mask it with the corresponding bits in the DMA
Interrupt Enable register to determine the source of the interrupt.
The bit allocation is given in
reserved
Description
reserved
GDMA Stop: When the GDMA_STOP command is issued to DMA Command registers, it
means that the DMA transfer has successfully terminated.
reserved
Internal EOT: Logic 1 indicates that an internal EOT is detected; see
reserved
DMA Transfer OK: Logic 1 indicates that the DMA transfer has been completed, that is,
DMA transfer counter has become zero.
reserved
Description
During the DMA transfer, there is a premature termination with short packet.
DMA transfer is completed with a short packet and the DMA transfer counter has reached 0.
DMA transfer is completed without any short packet and the DMA transfer counter has
reached 0.
R/W
R/W
14
0
0
6
0
0
R/W
R/W
13
0
0
5
0
0
Rev. 01 — 18 November 2009
Table
GDMA_
STOP
R/W
R/W
12
0
0
4
0
0
133.
reserved
reserved
[1]
R/W
R/W
11
0
0
3
0
0
INT_EOT
R/W
R/W
10
0
0
2
0
0
Hi-Speed USB OTG controller
reserved
R/W
R/W
Table
9
0
0
1
0
0
SAF1761
© NXP B.V. 2009. All rights reserved.
[1]
135.
XFER_OK
DMA_
118 of 166
R/W
R/W
8
0
0
0
0
0