SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 16

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 3.
SAF1761_1
Product data sheet
Port configuration
One port (port 1)
One port (port 2)
One port (port 3)
Two ports (ports 1
and 2)
Two ports (ports 2
and 3)
Two ports (ports 1
and 3)
Three ports (ports 1,
2 and 3)
Port connection scenarios
7.2.1 General considerations
7.2 Host controller buffer memory block
Port 1
DP and DM are routed to USB
connector
DP and DM are not connected
(left open)
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
DP and DM are routed to USB
connector
Port 2 does not need to be enabled by software, if only port 1 or port 3 is used. No port
needs to be disabled by external pull-up resistors, if not used. The DP and DM of the
unused ports need not be externally pulled HIGH because there are internal pull-down
resistors on each port that are enabled by default.
Table 3
The internal addressable host controller buffer memory is 63 kB. The 63 kB effective
memory size is the result of subtracting the size of the registers (1 kB) from the total
addressable memory space defined in the SAF1761 (64 kB). This is the optimized value
to achieve the highest performance with minimal cost.
The SAF1761 is a slave host controller. This means that it does not need access to the
local bus of the system to transfer data from the system memory to the SAF1761 internal
memory, unlike the case of the original PCI Hi-Speed USB host controllers. Therefore,
correct data must be transferred to both the PTD area and the payload area by PIO (using
CPU access) or programmed DMA.
The slave-host architecture ensures better compatibility with most of the processors
present in the market today because not all processors allow a bus-master on the local
bus. It also allows better load balancing of the processors local bus because only the
internal bus arbiter of the processor controls the transfer of data dedicated to USB. This
prevents the local bus from being busy when other more important transfers may be in the
queue; and therefore achieving a linear system data flow that has less impact on other
processes running at the same time.
The considerations mentioned are also the main reason for implementing the pre-fetching
technique, instead of using a READY signal. The resulting architecture avoids freezing of
the local bus, by asserting READY, enhancing the SAF1761 memory access time, and
avoiding introduction of programmed additional wait states. For details, see
lists the various port connection scenarios.
Rev. 01 — 18 November 2009
Port 2
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
DP and DM are routed to USB
connector
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
Hi-Speed USB OTG controller
Port 3
DP and DM are not connected
(left open)
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
DP and DM are not connected
(left open)
DP and DM are routed to USB
connector
DP and DM are routed to USB
connector
DP and DM are routed to USB
connector
SAF1761
© NXP B.V. 2009. All rights reserved.
Section
16 of 166
7.3.