SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 30

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SAF1761_1
Product data sheet
7.9 Power-On Reset (POR)
Figure 10
starts with a HIGH at t0. At t1, the detector will see the passing of the trip level V
and a delay element will add another t
t5 is too short, less than 11 ms, the PORP will not react and will remain LOW. A HIGH on
PORP will be generated whenever REG1V8 drops below V
The recommended RESET input pulse length at power-on must be at least 3 ms to ensure
that internal clocks are stable.
The RESET_N pin can be either connected to V
externally controlled by the microcontroller, ASIC, and so on.
availability of the clock with respect to the external POR.
Fig 10. Internal power-on reset timing
Fig 11. Clock with respect to the external power-on reset
(1) PORP = Power-On Reset Pulse.
Stable external clock is available at A.
t0
shows a possible curve of REG1V8 with dips at t2 to t3 and t4 to t5. The PORP
t
t1
PORP
Rev. 01 — 18 November 2009
EXTERNAL CLOCK
RESET_N
t2
PORP
before the PORP drops to 0. If the dip at t4 to
t
t3
PORP
CC(I/O)
A
using the internal POR circuit or
004aaa583
Hi-Speed USB OTG controller
t4
TRIP_LOW
Figure 11
t5
for more than 11 ms.
SAF1761
© NXP B.V. 2009. All rights reserved.
shows the
REG1V8
V
V
PORP
trip(H)
trip(L)
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TRIP_HIGH
(1)
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