SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 2

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SAF1761_1
Product data sheet
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Slave DMA implementation on CPU interface to reduce the host systems CPU load
Separate IRQ, DREQ and DACK lines for the host controller and the peripheral
controller
Integrated multi-configuration FIFO
Double-buffering scheme increases throughput and facilitates real-time data transfer
Integrated Phase-Locked Loop (PLL) with external 12 MHz crystal for low
ElectroMagnetic Interference (EMI)
Tolerant I/O for low voltage CPU interface (1.65 V to 3.3 V)
3.3 V-to-5.0 V external power supply input
Integrated 5.0 V-to-1.8 V or 3.3 V-to-1.8 V voltage regulator (internal 1.8 V for
low-power core)
Internal power-on reset or low-voltage reset and block-dedicated software reset
Supports suspend and remote wake-up
Built-in overcurrent circuitry (analog overcurrent protection)
Hybrid-power mode: V
Target total current consumption:
Host controller-specific features
OTG controller-specific features
Peripheral controller-specific features
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Normal operation; one port in high-speed active: I
charge pump is not used
Suspend mode: I
High performance USB host with integrated Hi-Speed USB transceivers; supports
high-speed, full-speed and low-speed
EHCI core is adapted from
Specification for Universal Serial Bus Rev. 1.0”
Configurable power management
Integrated TT for Original USB peripheral support on all three ports
Integrated 64 kB high-speed memory (internally organized as 8 k
Additional 2.5 kB separate memory for TT
Individual or global overcurrent protection with built-in sense circuits
Built-in overcurrent circuitry (digital or analog overcurrent protection)
OTG transceiver: fully integrated; adheres to
USB Specification Rev. 1.3”
Supports HNP and SRP for OTG dual-role devices
HNP: status and control registers for software implementation
SRP: status and control registers for software implementation
Programmable timers with high resolution (0.01 ms to 80 ms) for HNP and SRP
Supports external source of V
High-performance USB peripheral controller with integrated Serial Interface Engine
(SIE), FIFO memory and transceiver
Complies with
class specifications
Supports auto Hi-Speed USB mode discovery and Original USB fallback
capabilities
Supports high-speed and full-speed on the peripheral controller
Rev. 01 — 18 November 2009
Ref. 1 “Universal Serial Bus Specification Rev. 2.0”
CC(susp)
CC(5V0)
< 150 A at ambient temperature of +25 C
(can be switched off), V
Ref. 2 “Enhanced Host Controller Interface
BUS
Ref. 3 “On-The-Go Supplement to the
CC
CC(I/O)
Hi-Speed USB OTG controller
< 100 mA when the internal
(permanent)
SAF1761
© NXP B.V. 2009. All rights reserved.
and most device
64 bit)
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