SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 154

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SAF1761_1
Product data sheet
18.7.3 Workaround
The Peripheral Software driver needs to be modified to poll A_B_SESS_VLD bit in the
OTG Status Register (0x0378) instead of VBUSSTAT of the Mode Register (020Ch) to
detect the presence of the SAF1761 peripheral connection with USB Host. This bit has
lower trigger voltage.
To enable the setting of the A_B_SESS_VLD bit with V
functionality during the initialization of the SAF1761, see pseudo code below.
1761_Init()
{
}
Poll the A_B_SESS_VLD or Vbus_VLD bit to detect the connection with host and then
enable the DP pull up.
Connect_Thread()
{
}
Remark: Please take note of a limitation during SUSPEND; with this workaround
implementation, the SAF1761 Peripheral controller can enter into suspend. But it can
come out of suspend only with the Bus Reset from the host controller and cannot be
resumed using a normal RESUME signal.
Write32(0x0374, 0x0000400);
//OTG disabled need to check by removing this step in init
Write32(0x0374, 0x0400000); // OTG enabled
Write32(0x0374, 0x00160080); //Peripheral is enabled
UINT16 OTG_Stat_Reg = 0;
OTG_Stat_Reg = Read (0x0378);
If (OTG_Stat_Reg & 0x0002)
{
}
//Enable the soft-connect bit
Write32 (0x0374, 0x00000001);
Rev. 01 — 18 November 2009
BUS
, software needs to enable OTG
Hi-Speed USB OTG controller
SAF1761
© NXP B.V. 2009. All rights reserved.
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