SAF1761BE/V1,557 NXP Semiconductors, SAF1761BE/V1,557 Datasheet - Page 117

• Manufacturer Part Number: SAF1761BE/V1,557
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,557

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 130. DcDMAConfiguration - Device Controller Direct Memory Access Configuration register (address 0238h)
Table 131. DMA Hardware register (address 023Ch) bit allocation
[1]
Table 132. DMA Hardware register (address 023Ch) bit description
SAF1761_1
Product data sheet
Bit
3 to 2
1
0
Bit
Symbol
Reset
Bus reset
Access
Bit
7 to 6
5
4
3
2
1 to 0
The reserved bits should always be written with the reset value.
Symbol
-
DMA_XFER_EN DMA transfer enable: Write logic 1 to enable DMA transfer. Logic 0 disables the DMA transfer.
-
DACK_POL
DREQ_POL
-
bit description
Symbol
MODE[1:0]
-
WIDTH
10.5.5 DMA Hardware register
R/W
7
0
0
reserved
The DMA Hardware register consists of 1 byte. The bit allocation is shown in
This register determines the polarity of bus control signals (DACK and DREQ).
…continued
Description
reserved
reserved
DACK Polarity: Selects the DMA acknowledgment polarity.
0 — DACK is active LOW
1 — DACK is active HIGH
DREQ Polarity: Selects the DMA request polarity.
0 — DREQ is active LOW
1 — DREQ is active HIGH
reserved
[1]
R/W
6
0
0
Description
Mode:
00 — WR_N slave strobes data from the DMA bus into the SAF1761; RD_N slave puts
data from the SAF1761 on the DMA bus
01, 10, 11 — reserved
reserved
Width: This bit selects the DMA bus width for GDMA.
0 — 32-bit data bus
1 — 16-bit data bus
XFER_EN
DMA_
R/W
5
0
0
Rev. 01 — 18 November 2009
reserved
R/W
4
0
0
[1]
DACK_
POL
R/W
3
0
0
DREQ_
POL
R/W
2
1
1
Hi-Speed USB OTG controller
R/W
1
0
0
SAF1761
© NXP B.V. 2009. All rights reserved.
reserved
Table
[1]
117 of 166
R/W
0
0
0
131.