PSB3186FV14NT Infineon Technologies, PSB3186FV14NT Datasheet - Page 35

• Manufacturer Part Number: PSB3186FV14NT
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV14NT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

• C/I Code Change (Exchange Awake)
• EAW (Subscriber Awake)
• Watchdog Timer
After the selection of the watchdog timer (RSS = ’11’) an internal timer is reset and
started. During every time period of 128 ms the microcontroller has to program the
WTC1- and WTC2 bits in the following sequence to reset and restart the watchdog timer:
If not, the timer expires and a WOV-interrupt (ISTA Register) together with a reset pulse
of 125 µs is generated.
Deactivation of the watchdog timer is only possible with a hardware reset.
External Reset Input
At the RES input an external reset can be applied forcing the device in the reset state.
This external reset signal is additionally fed to the RSTO output. The length of the reset
signal is specified in
After an external reset from the RES pin all registers of the device are set to its reset
values (see register description in
Software Reset Register (SRES)
Every main functional block of the device can be reset separately by software setting the
corresponding bit in the SRES register. A reset to external devices can also be controlled
in this way. The reset state is activated by setting the corresponding bit to ’1’ and onchip
logic resets this bit again automatically after 4 BCL clock cycles. The address range of
the registers which will be reset at each SRES bit is listed in
3.2.5
The ISAC-SX TE provides two timers which can be used for various purposes. Each of
them provides two modes
generated only once after expiration of the selected period, and a periodic timer interrupt,
which means an interrupt is generated continuously after every expiration of that period.
Data Sheet
A change in the downstream C/I channel (C/I0) generates an external reset pulse of
125 µs £ t £ 250 µs.
A low level on the EAW input starts the oscillator from the power down state and
generates a reset pulse of 125 µs £ t £ 250 µs.
Timer Modes
1.
2.
Chapter
WTC1
1
0
(Table
5.8.
Chapter
7), a count down timer interrupt, i.e. an interrupt is
WTC2
0
1
35
4).
Description of Functional Blocks
Figure
9.
ISAC-SX TE
PSB 3186
2003-01-30