PSB3186FV14NT Infineon Technologies, PSB3186FV14NT Datasheet - Page 87

• Manufacturer Part Number: PSB3186FV14NT
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV14NT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

Figure 48
Before starting a transmission, the microprocessor should verify that the transmitter is
inactive, i.e. that a possible previous transmission has been terminated. This is indicated
by a ’0’ in the MONITOR Channel Active MAC status bit.
After having written the MONITOR Data Transmit (MOX) register, the microprocessor
sets the MONITOR Transmit Control bit MXC to ’1’. This enables the MX bit to go active
(0), indicating the presence of valid MONITOR data (contents of MOX) in the
corresponding frame. As a result, the receiving device stores the MONITOR byte in its
MONITOR Receive MOR register and generates an MDR interrupt status.
Alerted by the MDR interrupt, the microprocessor reads the MONITOR Receive (MOR)
register. When it is ready to accept data (e.g. based on the value in MOR, which in a
point-to-multipoint application might be the address of the destination device), it sets the
MR control bit MRC to ’1’ to enable the receiver to store succeeding MONITOR channel
bytes and acknowledge them according to the MONITOR channel protocol. In addition,
it enables other MONITOR channel interrupts by setting MONITOR Interrupt Enable
(MIE) to ’1’.
Data Sheet
MOX = DATA2
MOX = DATA1
MOX = ADR
MXC = 0
MAC = 0
MDA Int.
MDA Int.
MDA Int.
MXC = 1
MAC = 1
MIE = 1
P µ
MONITOR Channel Protocol (IOM-2)
MON
FF
FF
ADR
ADR
DATA1
DATA1
DATA1
DATA1
DATA2
DATA2
DATA2
DATA2
FF
FF
FF
FF
Transmitter
MX
1
1
0
0
1
0
0
0
1
0
0
0
1
1
1
1
87
Description of Functional Blocks
Receiver
MR
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
ITD10032
125 µ s
MDR Int.
RD MOR (=ADR)
MRC = 1
MDR Int.
RD MOR (=DATA1)
MDR Int.
RD MOR (=DATA2)
MER Int.
MRC = 0
µP
ISAC-SX TE
PSB 3186
2003-01-30